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- [197652]: [JSC] Improve codegen of Compare and Test ...
- ... org/show_bug.cgi?id=155055 Patch by Benjamin Poulain <bpoulain@apple.com> on 2016-03-06 Reviewed by Filip Pizlo. Source/JavaScriptCore: This patch introduces a few improvements on how we lower Compare and Test with immediates: -Add certain Immediate forms of ARM64. -Use CBZ/CBNZ when ...
- By Mar 6, 2016 6:40:16 PM —
- [197546]: [JSC] Add support for MADD, MSUB and MNEG to Air ...
- ... org/show_bug.cgi?id=154997 Patch by Benjamin Poulain <bpoulain@apple.com> on 2016-03-03 Reviewed by Filip Pizlo. ARM64 can do an Add/Sub in the Multiply units. LLVM was doing so but we lost that when switching to B3. This patch adds those instructions in Air. There are more ALUs than multip ...
- By Mar 3, 2016 8:40:17 PM —
- [197491]: [JSC] JSCell_freeListNext and JSCell_structureID are considered not ...
- ... org/show_bug.cgi?id=154947 Patch by Benjamin Poulain <bpoulain@apple.com> on 2016-03-02 Reviewed by Filip Pizlo. This bug was discovered while testing https://bugs.webkit.org/show_bug.cgi?id=154894. The problem was that JSCell_freeListNext and JSCell_structureID were considered as disjoint. ...
- By Mar 2, 2016 9:29:16 PM —
- [197490]: [JSC] Improve Select of Doubles based on Double condition ...
- ... org/show_bug.cgi?id=154572 Patch by Benjamin Poulain <bpoulain@apple.com> on 2016-03-02 Reviewed by Filip Pizlo. Octane has a bunch of Select on Double based on comparing Doubles. A few nodes generate that: ValueRep, Min, Max, etc. On ARM64, we can improve our code a lot. ARM can do a select ...
- By Mar 2, 2016 9:19:02 PM —
- [197446]: [JSC] Use a Move without REX byte when possible ...
- ... org/show_bug.cgi?id=154801 Patch by Benjamin Poulain <bpoulain@apple.com> on 2016-03-02 Reviewed by Alex Christensen. Filip wrote an optimization in the register allocator to use 32bit "Move" when we don't care about the top bytes. When I moved the commutative ops to the fake 3 operands inst ...
- By Mar 2, 2016 2:22:27 AM —
- [197329]: Merge r197186 - [JSC] Add32(Imm, Tmp, Tmp) does not ZDef the ...
- ... org/show_bug.cgi?id=154704 Patch by Benjamin Poulain <bpoulain@apple.com> on 2016-02-26 Reviewed by Geoffrey Garen. If the Imm is zero, we should still zero the top bits to match the definition in AirOpcodes. * assembler/MacroAssemblerX86Common.h: (JSC::MacroAssemblerX86Common::add32): * b3/ ...
- By Feb 29, 2016 2:23:51 AM —
- [197324]: Merge r197159 - [JSC] Be aggressive with OSR Entry to FTL if the DFG ...
- ... org/show_bug.cgi?id=154575 Patch by Benjamin Poulain <bpoulain@apple.com> on 2016-02-25 Reviewed by Filip Pizlo. I noticed that imaging-gaussian-blur spends most of its samples in DFG code despite executing most of the loop iterations in FTL. On this particular test, the main function is onl ...
- By Feb 29, 2016 2:02:16 AM —
- [197319]: Merge r197134 - [JSC] Remove a useless "Move" in the lowering of ...
- ... org/show_bug.cgi?id=154670 Patch by Benjamin Poulain <bpoulain@apple.com> on 2016-02-25 Reviewed by Geoffrey Garen. I left the Move instruction when creating the aliasing form of Select. On ARM64, that meant a useless move for any case that can't be coalesced. On x86, that meant an extra co ...
- By Feb 29, 2016 1:25:11 AM —
- [197186]: [JSC] Add32(Imm, Tmp, Tmp) does not ZDef the destination if Imm is ...
- ... org/show_bug.cgi?id=154704 Patch by Benjamin Poulain <bpoulain@apple.com> on 2016-02-26 Reviewed by Geoffrey Garen. If the Imm is zero, we should still zero the top bits to match the definition in AirOpcodes. * assembler/MacroAssemblerX86Common.h: (JSC::MacroAssemblerX86Common::add32): * b3/ ...
- By Feb 26, 2016 11:18:55 AM —
- [197159]: [JSC] Be aggressive with OSR Entry to FTL if the DFG function was only ...
- ... org/show_bug.cgi?id=154575 Patch by Benjamin Poulain <bpoulain@apple.com> on 2016-02-25 Reviewed by Filip Pizlo. I noticed that imaging-gaussian-blur spends most of its samples in DFG code despite executing most of the loop iterations in FTL. On this particular test, the main function is onl ...
- By Feb 25, 2016 9:59:48 PM —
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