Changeset 122594 in webkit


Ignore:
Timestamp:
Jul 13, 2012 9:35:46 AM (12 years ago)
Author:
Patrick Gansterer
Message:

Fix ARM_TRADITIONAL JIT for COMPILER(MSVC) and COMPILER(RVCT) after r121885
https://bugs.webkit.org/show_bug.cgi?id=91238

Reviewed by Zoltan Herczeg.

r121885 changed the assembler instruction only for COMPILER(GCC).
Use the same instructions for the other compilers too.

  • jit/JITStubs.cpp:

(JSC::ctiTrampoline):
(JSC::ctiTrampolineEnd):
(JSC::ctiVMThrowTrampoline):

Location:
trunk/Source/JavaScriptCore
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • trunk/Source/JavaScriptCore/ChangeLog

    r122544 r122594  
     12012-07-13  Patrick Gansterer  <paroga@webkit.org>
     2
     3        Fix ARM_TRADITIONAL JIT for COMPILER(MSVC) and COMPILER(RVCT) after r121885
     4        https://bugs.webkit.org/show_bug.cgi?id=91238
     5
     6        Reviewed by Zoltan Herczeg.
     7
     8        r121885 changed the assembler instruction only for COMPILER(GCC).
     9        Use the same instructions for the other compilers too.
     10
     11        * jit/JITStubs.cpp:
     12        (JSC::ctiTrampoline):
     13        (JSC::ctiTrampolineEnd):
     14        (JSC::ctiVMThrowTrampoline):
     15
    1162012-07-12  Filip Pizlo  <fpizlo@apple.com>
    217
  • trunk/Source/JavaScriptCore/jit/JITStubs.cpp

    r122206 r122594  
    741741    ARM
    742742    stmdb sp!, {r1-r3}
    743     stmdb sp!, {r4-r8, lr}
     743    stmdb sp!, {r4-r6, r8-r11, lr}
    744744    sub sp, sp, # PRESERVEDR4_OFFSET
    745     mov r4, r2
    746     mov r5, #512
     745    mov r5, r2
     746    mov r6, #512
    747747    mov lr, pc
    748748    bx r0
    749749    add sp, sp, # PRESERVEDR4_OFFSET
    750     ldmia sp!, {r4-r8, lr}
     750    ldmia sp!, {r4-r6, r8-r11, lr}
    751751    add sp, sp, #12
    752752    bx lr
     753}
     754__asm void ctiTrampolineEnd()
     755{
    753756}
    754757
     
    760763    bl cti_vm_throw
    761764    add sp, sp, # PRESERVEDR4_OFFSET
    762     ldmia sp!, {r4-r8, lr}
     765    ldmia sp!, {r4-r6, r8-r11, lr}
    763766    add sp, sp, #12
    764767    bx lr
     
    12131216MSVC_BEGIN()
    12141217MSVC_BEGIN(    EXPORT ctiTrampoline)
     1218MSVC_BEGIN(    EXPORT ctiTrampolineEnd)
    12151219MSVC_BEGIN(    EXPORT ctiVMThrowTrampoline)
    12161220MSVC_BEGIN(    EXPORT ctiOpThrowNotCaught)
     
    12181222MSVC_BEGIN(ctiTrampoline PROC)
    12191223MSVC_BEGIN(    stmdb sp!, {r1-r3})
    1220 MSVC_BEGIN(    stmdb sp!, {r4-r8, lr})
     1224MSVC_BEGIN(    stmdb sp!, {r4-r6, r8-r11, lr})
    12211225MSVC_BEGIN(    sub sp, sp, #68 ; sync with PRESERVEDR4_OFFSET)
    1222 MSVC_BEGIN(    mov r4, r2)
    1223 MSVC_BEGIN(    mov r5, #512)
     1226MSVC_BEGIN(    mov r5, r2)
     1227MSVC_BEGIN(    mov r6, #512)
    12241228MSVC_BEGIN(    ; r0 contains the code)
    12251229MSVC_BEGIN(    mov lr, pc)
    12261230MSVC_BEGIN(    bx r0)
    12271231MSVC_BEGIN(    add sp, sp, #68 ; sync with PRESERVEDR4_OFFSET)
    1228 MSVC_BEGIN(    ldmia sp!, {r4-r8, lr})
     1232MSVC_BEGIN(    ldmia sp!, {r4-r6, r8-r11, lr})
    12291233MSVC_BEGIN(    add sp, sp, #12)
    12301234MSVC_BEGIN(    bx lr)
     1235MSVC_BEGIN(ctiTrampolineEnd)
    12311236MSVC_BEGIN(ctiTrampoline ENDP)
    12321237MSVC_BEGIN()
    12331238MSVC_BEGIN(ctiVMThrowTrampoline PROC)
    12341239MSVC_BEGIN(    mov r0, sp)
    1235 MSVC_BEGIN(    mov lr, pc)
    12361240MSVC_BEGIN(    bl cti_vm_throw)
    12371241MSVC_BEGIN(ctiOpThrowNotCaught)
    12381242MSVC_BEGIN(    add sp, sp, #68 ; sync with PRESERVEDR4_OFFSET)
    1239 MSVC_BEGIN(    ldmia sp!, {r4-r8, lr})
     1243MSVC_BEGIN(    ldmia sp!, {r4-r6, r8-r11, lr})
    12401244MSVC_BEGIN(    add sp, sp, #12)
    12411245MSVC_BEGIN(    bx lr)
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