Changeset 125541 in webkit


Ignore:
Timestamp:
Aug 14, 2012 4:28:25 AM (12 years ago)
Author:
commit-queue@webkit.org
Message:

Rename functions in the ARM port of DFG-JIT for better code readability.
https://bugs.webkit.org/show_bug.cgi?id=93609

Patch by Gabor Ballabas <gaborb@inf.u-szeged.hu> on 2012-08-14
Reviewed by Zoltan Herczeg.

Rename functions in the ARM port of DFG-JIT for better code
readability, and for following the WebKit coding style
wherever it is possible.

  • assembler/ARMAssembler.cpp:

(JSC::ARMAssembler::genInt):
(JSC::ARMAssembler::getImm):
(JSC::ARMAssembler::moveImm):
(JSC::ARMAssembler::encodeComplexImm):
(JSC::ARMAssembler::dataTransfer32):
(JSC::ARMAssembler::baseIndexTransfer32):
(JSC::ARMAssembler::dataTransfer16):
(JSC::ARMAssembler::baseIndexTransfer16):
(JSC::ARMAssembler::dataTransferFloat):
(JSC::ARMAssembler::baseIndexTransferFloat):

  • assembler/ARMAssembler.h:

(JSC::ARMAssembler::bitAnd):
(JSC::ARMAssembler::bitAnds):
(JSC::ARMAssembler::eor):
(JSC::ARMAssembler::eors):
(JSC::ARMAssembler::sub):
(JSC::ARMAssembler::subs):
(JSC::ARMAssembler::rsb):
(JSC::ARMAssembler::rsbs):
(JSC::ARMAssembler::add):
(JSC::ARMAssembler::adds):
(JSC::ARMAssembler::adc):
(JSC::ARMAssembler::adcs):
(JSC::ARMAssembler::sbc):
(JSC::ARMAssembler::sbcs):
(JSC::ARMAssembler::rsc):
(JSC::ARMAssembler::rscs):
(JSC::ARMAssembler::tst):
(JSC::ARMAssembler::teq):
(JSC::ARMAssembler::cmp):
(JSC::ARMAssembler::cmn):
(JSC::ARMAssembler::orr):
(JSC::ARMAssembler::orrs):
(JSC::ARMAssembler::mov):
(JSC::ARMAssembler::movw):
(JSC::ARMAssembler::movt):
(JSC::ARMAssembler::movs):
(JSC::ARMAssembler::bic):
(JSC::ARMAssembler::bics):
(JSC::ARMAssembler::mvn):
(JSC::ARMAssembler::mvns):
(JSC::ARMAssembler::mul):
(JSC::ARMAssembler::muls):
(JSC::ARMAssembler::mull):
(JSC::ARMAssembler::vmov_f64):
(JSC::ARMAssembler::vadd_f64):
(JSC::ARMAssembler::vdiv_f64):
(JSC::ARMAssembler::vsub_f64):
(JSC::ARMAssembler::vmul_f64):
(JSC::ARMAssembler::vcmp_f64):
(JSC::ARMAssembler::vsqrt_f64):
(JSC::ARMAssembler::vabs_f64):
(JSC::ARMAssembler::vneg_f64):
(JSC::ARMAssembler::ldrImmediate):
(JSC::ARMAssembler::ldrUniqueImmediate):
(JSC::ARMAssembler::dtrUp):
(JSC::ARMAssembler::dtrUpRegister):
(JSC::ARMAssembler::dtrDown):
(JSC::ARMAssembler::dtrDownRegister):
(JSC::ARMAssembler::halfDtrUp):
(JSC::ARMAssembler::halfDtrUpRegister):
(JSC::ARMAssembler::halfDtrDown):
(JSC::ARMAssembler::halfDtrDownRegister):
(JSC::ARMAssembler::doubleDtrUp):
(JSC::ARMAssembler::doubleDtrDown):
(JSC::ARMAssembler::push):
(JSC::ARMAssembler::pop):
(JSC::ARMAssembler::poke):
(JSC::ARMAssembler::peek):
(JSC::ARMAssembler::vmov_vfp64):
(JSC::ARMAssembler::vmov_arm64):
(JSC::ARMAssembler::vmov_vfp32):
(JSC::ARMAssembler::vmov_arm32):
(JSC::ARMAssembler::vcvt_f64_s32):
(JSC::ARMAssembler::vcvt_s32_f64):
(JSC::ARMAssembler::vcvt_u32_f64):
(JSC::ARMAssembler::vcvt_f64_f32):
(JSC::ARMAssembler::vcvt_f32_f64):
(JSC::ARMAssembler::clz):
(JSC::ARMAssembler::lslRegister):
(JSC::ARMAssembler::lsrRegister):
(JSC::ARMAssembler::asrRegister):
(JSC::ARMAssembler::align):
(JSC::ARMAssembler::loadBranchTarget):
(JSC::ARMAssembler::vmov):

  • assembler/MacroAssemblerARM.cpp:

(JSC::MacroAssemblerARM::load32WithUnalignedHalfWords):

  • assembler/MacroAssemblerARM.h:

(JSC::MacroAssemblerARM::add32):
(JSC::MacroAssemblerARM::and32):
(JSC::MacroAssemblerARM::lshift32):
(JSC::MacroAssemblerARM::mul32):
(JSC::MacroAssemblerARM::or32):
(JSC::MacroAssemblerARM::rshift32):
(JSC::MacroAssemblerARM::urshift32):
(JSC::MacroAssemblerARM::sub32):
(JSC::MacroAssemblerARM::xor32):
(JSC::MacroAssemblerARM::countLeadingZeros32):
(JSC::MacroAssemblerARM::convertibleLoadPtr):
(JSC::MacroAssemblerARM::load32WithAddressOffsetPatch):
(JSC::MacroAssemblerARM::load32WithCompactAddressOffsetPatch):
(JSC::MacroAssemblerARM::store32WithAddressOffsetPatch):
(JSC::MacroAssemblerARM::store32):
(JSC::MacroAssemblerARM::pop):
(JSC::MacroAssemblerARM::push):
(JSC::MacroAssemblerARM::move):
(JSC::MacroAssemblerARM::swap):
(JSC::MacroAssemblerARM::branch32):
(JSC::MacroAssemblerARM::branchTest32):
(JSC::MacroAssemblerARM::mull32):
(JSC::MacroAssemblerARM::branchSub32):
(JSC::MacroAssemblerARM::compare32):
(JSC::MacroAssemblerARM::test32):
(JSC::MacroAssemblerARM::load32):
(JSC::MacroAssemblerARM::relativeTableJump):
(JSC::MacroAssemblerARM::moveWithPatch):
(JSC::MacroAssemblerARM::loadDouble):
(JSC::MacroAssemblerARM::moveDouble):
(JSC::MacroAssemblerARM::addDouble):
(JSC::MacroAssemblerARM::divDouble):
(JSC::MacroAssemblerARM::subDouble):
(JSC::MacroAssemblerARM::mulDouble):
(JSC::MacroAssemblerARM::sqrtDouble):
(JSC::MacroAssemblerARM::absDouble):
(JSC::MacroAssemblerARM::negateDouble):
(JSC::MacroAssemblerARM::convertInt32ToDouble):
(JSC::MacroAssemblerARM::convertFloatToDouble):
(JSC::MacroAssemblerARM::convertDoubleToFloat):
(JSC::MacroAssemblerARM::branchDouble):
(JSC::MacroAssemblerARM::branchTruncateDoubleToInt32):
(JSC::MacroAssemblerARM::branchTruncateDoubleToUint32):
(JSC::MacroAssemblerARM::truncateDoubleToInt32):
(JSC::MacroAssemblerARM::truncateDoubleToUint32):
(JSC::MacroAssemblerARM::branchConvertDoubleToInt32):
(JSC::MacroAssemblerARM::branchDoubleNonZero):
(JSC::MacroAssemblerARM::branchDoubleZeroOrNaN):

Location:
trunk/Source/JavaScriptCore
Files:
5 edited

Legend:

Unmodified
Added
Removed
  • trunk/Source/JavaScriptCore/ChangeLog

    r125452 r125541  
     12012-08-14  Gabor Ballabas  <gaborb@inf.u-szeged.hu>
     2
     3        Rename functions in the ARM port of DFG-JIT for better code readability.
     4        https://bugs.webkit.org/show_bug.cgi?id=93609
     5
     6        Reviewed by Zoltan Herczeg.
     7
     8        Rename functions in the ARM port of DFG-JIT for better code
     9        readability, and for following the WebKit coding style
     10        wherever it is possible.
     11
     12        * assembler/ARMAssembler.cpp:
     13        (JSC::ARMAssembler::genInt):
     14        (JSC::ARMAssembler::getImm):
     15        (JSC::ARMAssembler::moveImm):
     16        (JSC::ARMAssembler::encodeComplexImm):
     17        (JSC::ARMAssembler::dataTransfer32):
     18        (JSC::ARMAssembler::baseIndexTransfer32):
     19        (JSC::ARMAssembler::dataTransfer16):
     20        (JSC::ARMAssembler::baseIndexTransfer16):
     21        (JSC::ARMAssembler::dataTransferFloat):
     22        (JSC::ARMAssembler::baseIndexTransferFloat):
     23        * assembler/ARMAssembler.h:
     24        (JSC::ARMAssembler::bitAnd):
     25        (JSC::ARMAssembler::bitAnds):
     26        (JSC::ARMAssembler::eor):
     27        (JSC::ARMAssembler::eors):
     28        (JSC::ARMAssembler::sub):
     29        (JSC::ARMAssembler::subs):
     30        (JSC::ARMAssembler::rsb):
     31        (JSC::ARMAssembler::rsbs):
     32        (JSC::ARMAssembler::add):
     33        (JSC::ARMAssembler::adds):
     34        (JSC::ARMAssembler::adc):
     35        (JSC::ARMAssembler::adcs):
     36        (JSC::ARMAssembler::sbc):
     37        (JSC::ARMAssembler::sbcs):
     38        (JSC::ARMAssembler::rsc):
     39        (JSC::ARMAssembler::rscs):
     40        (JSC::ARMAssembler::tst):
     41        (JSC::ARMAssembler::teq):
     42        (JSC::ARMAssembler::cmp):
     43        (JSC::ARMAssembler::cmn):
     44        (JSC::ARMAssembler::orr):
     45        (JSC::ARMAssembler::orrs):
     46        (JSC::ARMAssembler::mov):
     47        (JSC::ARMAssembler::movw):
     48        (JSC::ARMAssembler::movt):
     49        (JSC::ARMAssembler::movs):
     50        (JSC::ARMAssembler::bic):
     51        (JSC::ARMAssembler::bics):
     52        (JSC::ARMAssembler::mvn):
     53        (JSC::ARMAssembler::mvns):
     54        (JSC::ARMAssembler::mul):
     55        (JSC::ARMAssembler::muls):
     56        (JSC::ARMAssembler::mull):
     57        (JSC::ARMAssembler::vmov_f64):
     58        (JSC::ARMAssembler::vadd_f64):
     59        (JSC::ARMAssembler::vdiv_f64):
     60        (JSC::ARMAssembler::vsub_f64):
     61        (JSC::ARMAssembler::vmul_f64):
     62        (JSC::ARMAssembler::vcmp_f64):
     63        (JSC::ARMAssembler::vsqrt_f64):
     64        (JSC::ARMAssembler::vabs_f64):
     65        (JSC::ARMAssembler::vneg_f64):
     66        (JSC::ARMAssembler::ldrImmediate):
     67        (JSC::ARMAssembler::ldrUniqueImmediate):
     68        (JSC::ARMAssembler::dtrUp):
     69        (JSC::ARMAssembler::dtrUpRegister):
     70        (JSC::ARMAssembler::dtrDown):
     71        (JSC::ARMAssembler::dtrDownRegister):
     72        (JSC::ARMAssembler::halfDtrUp):
     73        (JSC::ARMAssembler::halfDtrUpRegister):
     74        (JSC::ARMAssembler::halfDtrDown):
     75        (JSC::ARMAssembler::halfDtrDownRegister):
     76        (JSC::ARMAssembler::doubleDtrUp):
     77        (JSC::ARMAssembler::doubleDtrDown):
     78        (JSC::ARMAssembler::push):
     79        (JSC::ARMAssembler::pop):
     80        (JSC::ARMAssembler::poke):
     81        (JSC::ARMAssembler::peek):
     82        (JSC::ARMAssembler::vmov_vfp64):
     83        (JSC::ARMAssembler::vmov_arm64):
     84        (JSC::ARMAssembler::vmov_vfp32):
     85        (JSC::ARMAssembler::vmov_arm32):
     86        (JSC::ARMAssembler::vcvt_f64_s32):
     87        (JSC::ARMAssembler::vcvt_s32_f64):
     88        (JSC::ARMAssembler::vcvt_u32_f64):
     89        (JSC::ARMAssembler::vcvt_f64_f32):
     90        (JSC::ARMAssembler::vcvt_f32_f64):
     91        (JSC::ARMAssembler::clz):
     92        (JSC::ARMAssembler::lslRegister):
     93        (JSC::ARMAssembler::lsrRegister):
     94        (JSC::ARMAssembler::asrRegister):
     95        (JSC::ARMAssembler::align):
     96        (JSC::ARMAssembler::loadBranchTarget):
     97        (JSC::ARMAssembler::vmov):
     98        * assembler/MacroAssemblerARM.cpp:
     99        (JSC::MacroAssemblerARM::load32WithUnalignedHalfWords):
     100        * assembler/MacroAssemblerARM.h:
     101        (JSC::MacroAssemblerARM::add32):
     102        (JSC::MacroAssemblerARM::and32):
     103        (JSC::MacroAssemblerARM::lshift32):
     104        (JSC::MacroAssemblerARM::mul32):
     105        (JSC::MacroAssemblerARM::or32):
     106        (JSC::MacroAssemblerARM::rshift32):
     107        (JSC::MacroAssemblerARM::urshift32):
     108        (JSC::MacroAssemblerARM::sub32):
     109        (JSC::MacroAssemblerARM::xor32):
     110        (JSC::MacroAssemblerARM::countLeadingZeros32):
     111        (JSC::MacroAssemblerARM::convertibleLoadPtr):
     112        (JSC::MacroAssemblerARM::load32WithAddressOffsetPatch):
     113        (JSC::MacroAssemblerARM::load32WithCompactAddressOffsetPatch):
     114        (JSC::MacroAssemblerARM::store32WithAddressOffsetPatch):
     115        (JSC::MacroAssemblerARM::store32):
     116        (JSC::MacroAssemblerARM::pop):
     117        (JSC::MacroAssemblerARM::push):
     118        (JSC::MacroAssemblerARM::move):
     119        (JSC::MacroAssemblerARM::swap):
     120        (JSC::MacroAssemblerARM::branch32):
     121        (JSC::MacroAssemblerARM::branchTest32):
     122        (JSC::MacroAssemblerARM::mull32):
     123        (JSC::MacroAssemblerARM::branchSub32):
     124        (JSC::MacroAssemblerARM::compare32):
     125        (JSC::MacroAssemblerARM::test32):
     126        (JSC::MacroAssemblerARM::load32):
     127        (JSC::MacroAssemblerARM::relativeTableJump):
     128        (JSC::MacroAssemblerARM::moveWithPatch):
     129        (JSC::MacroAssemblerARM::loadDouble):
     130        (JSC::MacroAssemblerARM::moveDouble):
     131        (JSC::MacroAssemblerARM::addDouble):
     132        (JSC::MacroAssemblerARM::divDouble):
     133        (JSC::MacroAssemblerARM::subDouble):
     134        (JSC::MacroAssemblerARM::mulDouble):
     135        (JSC::MacroAssemblerARM::sqrtDouble):
     136        (JSC::MacroAssemblerARM::absDouble):
     137        (JSC::MacroAssemblerARM::negateDouble):
     138        (JSC::MacroAssemblerARM::convertInt32ToDouble):
     139        (JSC::MacroAssemblerARM::convertFloatToDouble):
     140        (JSC::MacroAssemblerARM::convertDoubleToFloat):
     141        (JSC::MacroAssemblerARM::branchDouble):
     142        (JSC::MacroAssemblerARM::branchTruncateDoubleToInt32):
     143        (JSC::MacroAssemblerARM::branchTruncateDoubleToUint32):
     144        (JSC::MacroAssemblerARM::truncateDoubleToInt32):
     145        (JSC::MacroAssemblerARM::truncateDoubleToUint32):
     146        (JSC::MacroAssemblerARM::branchConvertDoubleToInt32):
     147        (JSC::MacroAssemblerARM::branchDoubleNonZero):
     148        (JSC::MacroAssemblerARM::branchDoubleZeroOrNaN):
     149
    11502012-08-13  Simon Hausmann  <simon.hausmann@nokia.com>
    2151
  • trunk/Source/JavaScriptCore/assembler/ARMAssembler.cpp

    r124930 r125541  
    188188
    189189    if (positive) {
    190         mov_r(reg, imm1);
    191         orr_r(reg, reg, imm2);
     190        mov(reg, imm1);
     191        orr(reg, reg, imm2);
    192192    } else {
    193         mvn_r(reg, imm1);
    194         bic_r(reg, reg, imm2);
     193        mvn(reg, imm1);
     194        bic(reg, reg, imm2);
    195195    }
    196196
     
    211211        if (invert)
    212212            return tmp | Op2InvertedImmediate;
    213         mvn_r(tmpReg, tmp);
     213        mvn(tmpReg, tmp);
    214214        return tmpReg;
    215215    }
     
    225225    tmp = getOp2(imm);
    226226    if (tmp != InvalidImmediate) {
    227         mov_r(dest, tmp);
     227        mov(dest, tmp);
    228228        return;
    229229    }
     
    231231    tmp = getOp2(~imm);
    232232    if (tmp != InvalidImmediate) {
    233         mvn_r(dest, tmp);
     233        mvn(dest, tmp);
    234234        return;
    235235    }
     
    243243    ARMWord tmp = getImm16Op2(imm);
    244244    if (tmp != InvalidImmediate) {
    245         movw_r(dest, tmp);
     245        movw(dest, tmp);
    246246        return dest;
    247247    }
    248     movw_r(dest, getImm16Op2(imm & 0xffff));
    249     movt_r(dest, getImm16Op2(imm >> 16));
     248    movw(dest, getImm16Op2(imm & 0xffff));
     249    movt(dest, getImm16Op2(imm >> 16));
    250250    return dest;
    251251#else
     
    256256        return dest;
    257257
    258     ldr_imm(dest, imm);
     258    ldrImmediate(dest, imm);
    259259    return dest;
    260260#endif
     
    267267    if (offset >= 0) {
    268268        if (offset <= 0xfff)
    269             dtr_u(transferType, srcDst, base, offset);
     269            dtrUp(transferType, srcDst, base, offset);
    270270        else if (offset <= 0xfffff) {
    271             add_r(ARMRegisters::S0, base, Op2Immediate | (offset >> 12) | (10 << 8));
    272             dtr_u(transferType, srcDst, ARMRegisters::S0, (offset & 0xfff));
     271            add(ARMRegisters::S0, base, Op2Immediate | (offset >> 12) | (10 << 8));
     272            dtrUp(transferType, srcDst, ARMRegisters::S0, (offset & 0xfff));
    273273        } else {
    274274            moveImm(offset, ARMRegisters::S0);
    275             dtr_ur(transferType, srcDst, base, ARMRegisters::S0);
     275            dtrUpRegister(transferType, srcDst, base, ARMRegisters::S0);
    276276        }
    277277    } else {
    278278        if (offset >= -0xfff)
    279             dtr_d(transferType, srcDst, base, -offset);
     279            dtrDown(transferType, srcDst, base, -offset);
    280280        else if (offset >= -0xfffff) {
    281             sub_r(ARMRegisters::S0, base, Op2Immediate | (-offset >> 12) | (10 << 8));
    282             dtr_d(transferType, srcDst, ARMRegisters::S0, (-offset & 0xfff));
     281            sub(ARMRegisters::S0, base, Op2Immediate | (-offset >> 12) | (10 << 8));
     282            dtrDown(transferType, srcDst, ARMRegisters::S0, (-offset & 0xfff));
    283283        } else {
    284284            moveImm(offset, ARMRegisters::S0);
    285             dtr_ur(transferType, srcDst, base, ARMRegisters::S0);
     285            dtrUpRegister(transferType, srcDst, base, ARMRegisters::S0);
    286286        }
    287287    }
     
    294294
    295295    if (!offset) {
    296         dtr_ur(transferType, srcDst, base, op2);
     296        dtrUpRegister(transferType, srcDst, base, op2);
    297297        return;
    298298    }
    299299
    300     add_r(ARMRegisters::S1, base, op2);
     300    add(ARMRegisters::S1, base, op2);
    301301    dataTransfer32(transferType, srcDst, ARMRegisters::S1, offset);
    302302}
     
    306306    if (offset >= 0) {
    307307        if (offset <= 0xff)
    308             dtrh_u(transferType, srcDst, base, getOp2Half(offset));
     308            halfDtrUp(transferType, srcDst, base, getOp2Half(offset));
    309309        else if (offset <= 0xffff) {
    310             add_r(ARMRegisters::S0, base, Op2Immediate | (offset >> 8) | (12 << 8));
    311             dtrh_u(transferType, srcDst, ARMRegisters::S0, getOp2Half(offset & 0xff));
     310            add(ARMRegisters::S0, base, Op2Immediate | (offset >> 8) | (12 << 8));
     311            halfDtrUp(transferType, srcDst, ARMRegisters::S0, getOp2Half(offset & 0xff));
    312312        } else {
    313313            moveImm(offset, ARMRegisters::S0);
    314             dtrh_ur(transferType, srcDst, base, ARMRegisters::S0);
     314            halfDtrUpRegister(transferType, srcDst, base, ARMRegisters::S0);
    315315        }
    316316    } else {
    317317        if (offset >= -0xff)
    318             dtrh_d(transferType, srcDst, base, getOp2Half(-offset));
     318            halfDtrDown(transferType, srcDst, base, getOp2Half(-offset));
    319319        else if (offset >= -0xffff) {
    320             sub_r(ARMRegisters::S0, base, Op2Immediate | (-offset >> 8) | (12 << 8));
    321             dtrh_d(transferType, srcDst, ARMRegisters::S0, getOp2Half(-offset & 0xff));
     320            sub(ARMRegisters::S0, base, Op2Immediate | (-offset >> 8) | (12 << 8));
     321            halfDtrDown(transferType, srcDst, ARMRegisters::S0, getOp2Half(-offset & 0xff));
    322322        } else {
    323323            moveImm(offset, ARMRegisters::S0);
    324             dtrh_ur(transferType, srcDst, base, ARMRegisters::S0);
     324            halfDtrUpRegister(transferType, srcDst, base, ARMRegisters::S0);
    325325        }
    326326    }
     
    330330{
    331331    if (!scale && !offset) {
    332         dtrh_ur(transferType, srcDst, base, index);
     332        halfDtrUpRegister(transferType, srcDst, base, index);
    333333        return;
    334334    }
    335335
    336     add_r(ARMRegisters::S1, base, lsl(index, scale));
     336    add(ARMRegisters::S1, base, lsl(index, scale));
    337337    dataTransfer16(transferType, srcDst, ARMRegisters::S1, offset);
    338338}
     
    343343    if (!(offset & 0x3)) {
    344344        if (offset <= 0x3ff && offset >= 0) {
    345             fdtr_u(transferType, srcDst, base, offset >> 2);
     345            doubleDtrUp(transferType, srcDst, base, offset >> 2);
    346346            return;
    347347        }
    348348        if (offset <= 0x3ffff && offset >= 0) {
    349             add_r(ARMRegisters::S0, base, Op2Immediate | (offset >> 10) | (11 << 8));
    350             fdtr_u(transferType, srcDst, ARMRegisters::S0, (offset >> 2) & 0xff);
     349            add(ARMRegisters::S0, base, Op2Immediate | (offset >> 10) | (11 << 8));
     350            doubleDtrUp(transferType, srcDst, ARMRegisters::S0, (offset >> 2) & 0xff);
    351351            return;
    352352        }
     
    354354
    355355        if (offset <= 0x3ff && offset >= 0) {
    356             fdtr_d(transferType, srcDst, base, offset >> 2);
     356            doubleDtrDown(transferType, srcDst, base, offset >> 2);
    357357            return;
    358358        }
    359359        if (offset <= 0x3ffff && offset >= 0) {
    360             sub_r(ARMRegisters::S0, base, Op2Immediate | (offset >> 10) | (11 << 8));
    361             fdtr_d(transferType, srcDst, ARMRegisters::S0, (offset >> 2) & 0xff);
     360            sub(ARMRegisters::S0, base, Op2Immediate | (offset >> 10) | (11 << 8));
     361            doubleDtrDown(transferType, srcDst, ARMRegisters::S0, (offset >> 2) & 0xff);
    362362            return;
    363363        }
     
    366366
    367367    moveImm(offset, ARMRegisters::S0);
    368     add_r(ARMRegisters::S0, ARMRegisters::S0, base);
    369     fdtr_u(transferType, srcDst, ARMRegisters::S0, 0);
     368    add(ARMRegisters::S0, ARMRegisters::S0, base);
     369    doubleDtrUp(transferType, srcDst, ARMRegisters::S0, 0);
    370370}
    371371
    372372void ARMAssembler::baseIndexTransferFloat(DataTransferTypeFloat transferType, FPRegisterID srcDst, RegisterID base, RegisterID index, int scale, int32_t offset)
    373373{
    374     add_r(ARMRegisters::S1, base, lsl(index, scale));
     374    add(ARMRegisters::S1, base, lsl(index, scale));
    375375    dataTransferFloat(transferType, srcDst, ARMRegisters::S1, offset);
    376376}
  • trunk/Source/JavaScriptCore/assembler/ARMAssembler.h

    r124930 r125541  
    269269        }
    270270
    271         void and_r(int rd, int rn, ARMWord op2, Condition cc = AL)
     271        void bitAnd(int rd, int rn, ARMWord op2, Condition cc = AL)
    272272        {
    273273            emitInstruction(toARMWord(cc) | AND, rd, rn, op2);
    274274        }
    275275
    276         void ands_r(int rd, int rn, ARMWord op2, Condition cc = AL)
     276        void bitAnds(int rd, int rn, ARMWord op2, Condition cc = AL)
    277277        {
    278278            emitInstruction(toARMWord(cc) | AND | SetConditionalCodes, rd, rn, op2);
    279279        }
    280280
    281         void eor_r(int rd, int rn, ARMWord op2, Condition cc = AL)
     281        void eor(int rd, int rn, ARMWord op2, Condition cc = AL)
    282282        {
    283283            emitInstruction(toARMWord(cc) | EOR, rd, rn, op2);
    284284        }
    285285
    286         void eors_r(int rd, int rn, ARMWord op2, Condition cc = AL)
     286        void eors(int rd, int rn, ARMWord op2, Condition cc = AL)
    287287        {
    288288            emitInstruction(toARMWord(cc) | EOR | SetConditionalCodes, rd, rn, op2);
    289289        }
    290290
    291         void sub_r(int rd, int rn, ARMWord op2, Condition cc = AL)
     291        void sub(int rd, int rn, ARMWord op2, Condition cc = AL)
    292292        {
    293293            emitInstruction(toARMWord(cc) | SUB, rd, rn, op2);
    294294        }
    295295
    296         void subs_r(int rd, int rn, ARMWord op2, Condition cc = AL)
     296        void subs(int rd, int rn, ARMWord op2, Condition cc = AL)
    297297        {
    298298            emitInstruction(toARMWord(cc) | SUB | SetConditionalCodes, rd, rn, op2);
    299299        }
    300300
    301         void rsb_r(int rd, int rn, ARMWord op2, Condition cc = AL)
     301        void rsb(int rd, int rn, ARMWord op2, Condition cc = AL)
    302302        {
    303303            emitInstruction(toARMWord(cc) | RSB, rd, rn, op2);
    304304        }
    305305
    306         void rsbs_r(int rd, int rn, ARMWord op2, Condition cc = AL)
     306        void rsbs(int rd, int rn, ARMWord op2, Condition cc = AL)
    307307        {
    308308            emitInstruction(toARMWord(cc) | RSB | SetConditionalCodes, rd, rn, op2);
    309309        }
    310310
    311         void add_r(int rd, int rn, ARMWord op2, Condition cc = AL)
     311        void add(int rd, int rn, ARMWord op2, Condition cc = AL)
    312312        {
    313313            emitInstruction(toARMWord(cc) | ADD, rd, rn, op2);
    314314        }
    315315
    316         void adds_r(int rd, int rn, ARMWord op2, Condition cc = AL)
     316        void adds(int rd, int rn, ARMWord op2, Condition cc = AL)
    317317        {
    318318            emitInstruction(toARMWord(cc) | ADD | SetConditionalCodes, rd, rn, op2);
    319319        }
    320320
    321         void adc_r(int rd, int rn, ARMWord op2, Condition cc = AL)
     321        void adc(int rd, int rn, ARMWord op2, Condition cc = AL)
    322322        {
    323323            emitInstruction(toARMWord(cc) | ADC, rd, rn, op2);
    324324        }
    325325
    326         void adcs_r(int rd, int rn, ARMWord op2, Condition cc = AL)
     326        void adcs(int rd, int rn, ARMWord op2, Condition cc = AL)
    327327        {
    328328            emitInstruction(toARMWord(cc) | ADC | SetConditionalCodes, rd, rn, op2);
    329329        }
    330330
    331         void sbc_r(int rd, int rn, ARMWord op2, Condition cc = AL)
     331        void sbc(int rd, int rn, ARMWord op2, Condition cc = AL)
    332332        {
    333333            emitInstruction(toARMWord(cc) | SBC, rd, rn, op2);
    334334        }
    335335
    336         void sbcs_r(int rd, int rn, ARMWord op2, Condition cc = AL)
     336        void sbcs(int rd, int rn, ARMWord op2, Condition cc = AL)
    337337        {
    338338            emitInstruction(toARMWord(cc) | SBC | SetConditionalCodes, rd, rn, op2);
    339339        }
    340340
    341         void rsc_r(int rd, int rn, ARMWord op2, Condition cc = AL)
     341        void rsc(int rd, int rn, ARMWord op2, Condition cc = AL)
    342342        {
    343343            emitInstruction(toARMWord(cc) | RSC, rd, rn, op2);
    344344        }
    345345
    346         void rscs_r(int rd, int rn, ARMWord op2, Condition cc = AL)
     346        void rscs(int rd, int rn, ARMWord op2, Condition cc = AL)
    347347        {
    348348            emitInstruction(toARMWord(cc) | RSC | SetConditionalCodes, rd, rn, op2);
    349349        }
    350350
    351         void tst_r(int rn, ARMWord op2, Condition cc = AL)
     351        void tst(int rn, ARMWord op2, Condition cc = AL)
    352352        {
    353353            emitInstruction(toARMWord(cc) | TST | SetConditionalCodes, 0, rn, op2);
    354354        }
    355355
    356         void teq_r(int rn, ARMWord op2, Condition cc = AL)
     356        void teq(int rn, ARMWord op2, Condition cc = AL)
    357357        {
    358358            emitInstruction(toARMWord(cc) | TEQ | SetConditionalCodes, 0, rn, op2);
    359359        }
    360360
    361         void cmp_r(int rn, ARMWord op2, Condition cc = AL)
     361        void cmp(int rn, ARMWord op2, Condition cc = AL)
    362362        {
    363363            emitInstruction(toARMWord(cc) | CMP | SetConditionalCodes, 0, rn, op2);
    364364        }
    365365
    366         void cmn_r(int rn, ARMWord op2, Condition cc = AL)
     366        void cmn(int rn, ARMWord op2, Condition cc = AL)
    367367        {
    368368            emitInstruction(toARMWord(cc) | CMN | SetConditionalCodes, 0, rn, op2);
    369369        }
    370370
    371         void orr_r(int rd, int rn, ARMWord op2, Condition cc = AL)
     371        void orr(int rd, int rn, ARMWord op2, Condition cc = AL)
    372372        {
    373373            emitInstruction(toARMWord(cc) | ORR, rd, rn, op2);
    374374        }
    375375
    376         void orrs_r(int rd, int rn, ARMWord op2, Condition cc = AL)
     376        void orrs(int rd, int rn, ARMWord op2, Condition cc = AL)
    377377        {
    378378            emitInstruction(toARMWord(cc) | ORR | SetConditionalCodes, rd, rn, op2);
    379379        }
    380380
    381         void mov_r(int rd, ARMWord op2, Condition cc = AL)
     381        void mov(int rd, ARMWord op2, Condition cc = AL)
    382382        {
    383383            emitInstruction(toARMWord(cc) | MOV, rd, ARMRegisters::r0, op2);
     
    385385
    386386#if WTF_ARM_ARCH_AT_LEAST(7)
    387         void movw_r(int rd, ARMWord op2, Condition cc = AL)
     387        void movw(int rd, ARMWord op2, Condition cc = AL)
    388388        {
    389389            ASSERT((op2 | 0xf0fff) == 0xf0fff);
     
    391391        }
    392392
    393         void movt_r(int rd, ARMWord op2, Condition cc = AL)
     393        void movt(int rd, ARMWord op2, Condition cc = AL)
    394394        {
    395395            ASSERT((op2 | 0xf0fff) == 0xf0fff);
     
    398398#endif
    399399
    400         void movs_r(int rd, ARMWord op2, Condition cc = AL)
     400        void movs(int rd, ARMWord op2, Condition cc = AL)
    401401        {
    402402            emitInstruction(toARMWord(cc) | MOV | SetConditionalCodes, rd, ARMRegisters::r0, op2);
    403403        }
    404404
    405         void bic_r(int rd, int rn, ARMWord op2, Condition cc = AL)
     405        void bic(int rd, int rn, ARMWord op2, Condition cc = AL)
    406406        {
    407407            emitInstruction(toARMWord(cc) | BIC, rd, rn, op2);
    408408        }
    409409
    410         void bics_r(int rd, int rn, ARMWord op2, Condition cc = AL)
     410        void bics(int rd, int rn, ARMWord op2, Condition cc = AL)
    411411        {
    412412            emitInstruction(toARMWord(cc) | BIC | SetConditionalCodes, rd, rn, op2);
    413413        }
    414414
    415         void mvn_r(int rd, ARMWord op2, Condition cc = AL)
     415        void mvn(int rd, ARMWord op2, Condition cc = AL)
    416416        {
    417417            emitInstruction(toARMWord(cc) | MVN, rd, ARMRegisters::r0, op2);
    418418        }
    419419
    420         void mvns_r(int rd, ARMWord op2, Condition cc = AL)
     420        void mvns(int rd, ARMWord op2, Condition cc = AL)
    421421        {
    422422            emitInstruction(toARMWord(cc) | MVN | SetConditionalCodes, rd, ARMRegisters::r0, op2);
    423423        }
    424424
    425         void mul_r(int rd, int rn, int rm, Condition cc = AL)
     425        void mul(int rd, int rn, int rm, Condition cc = AL)
    426426        {
    427427            m_buffer.putInt(toARMWord(cc) | MUL | RN(rd) | RS(rn) | RM(rm));
    428428        }
    429429
    430         void muls_r(int rd, int rn, int rm, Condition cc = AL)
     430        void muls(int rd, int rn, int rm, Condition cc = AL)
    431431        {
    432432            m_buffer.putInt(toARMWord(cc) | MUL | SetConditionalCodes | RN(rd) | RS(rn) | RM(rm));
    433433        }
    434434
    435         void mull_r(int rdhi, int rdlo, int rn, int rm, Condition cc = AL)
     435        void mull(int rdhi, int rdlo, int rn, int rm, Condition cc = AL)
    436436        {
    437437            m_buffer.putInt(toARMWord(cc) | MULL | RN(rdhi) | RD(rdlo) | RS(rn) | RM(rm));
    438438        }
    439439
    440         void vmov_f64_r(int dd, int dm, Condition cc = AL)
     440        void vmov_f64(int dd, int dm, Condition cc = AL)
    441441        {
    442442            emitDoublePrecisionInstruction(toARMWord(cc) | VMOV_F64, dd, 0, dm);
    443443        }
    444444
    445         void vadd_f64_r(int dd, int dn, int dm, Condition cc = AL)
     445        void vadd_f64(int dd, int dn, int dm, Condition cc = AL)
    446446        {
    447447            emitDoublePrecisionInstruction(toARMWord(cc) | VADD_F64, dd, dn, dm);
    448448        }
    449449
    450         void vdiv_f64_r(int dd, int dn, int dm, Condition cc = AL)
     450        void vdiv_f64(int dd, int dn, int dm, Condition cc = AL)
    451451        {
    452452            emitDoublePrecisionInstruction(toARMWord(cc) | VDIV_F64, dd, dn, dm);
    453453        }
    454454
    455         void vsub_f64_r(int dd, int dn, int dm, Condition cc = AL)
     455        void vsub_f64(int dd, int dn, int dm, Condition cc = AL)
    456456        {
    457457            emitDoublePrecisionInstruction(toARMWord(cc) | VSUB_F64, dd, dn, dm);
    458458        }
    459459
    460         void vmul_f64_r(int dd, int dn, int dm, Condition cc = AL)
     460        void vmul_f64(int dd, int dn, int dm, Condition cc = AL)
    461461        {
    462462            emitDoublePrecisionInstruction(toARMWord(cc) | VMUL_F64, dd, dn, dm);
    463463        }
    464464
    465         void vcmp_f64_r(int dd, int dm, Condition cc = AL)
     465        void vcmp_f64(int dd, int dm, Condition cc = AL)
    466466        {
    467467            emitDoublePrecisionInstruction(toARMWord(cc) | VCMP_F64, dd, 0, dm);
    468468        }
    469469
    470         void vsqrt_f64_r(int dd, int dm, Condition cc = AL)
     470        void vsqrt_f64(int dd, int dm, Condition cc = AL)
    471471        {
    472472            emitDoublePrecisionInstruction(toARMWord(cc) | VSQRT_F64, dd, 0, dm);
    473473        }
    474474
    475         void vabs_f64_r(int dd, int dm, Condition cc = AL)
     475        void vabs_f64(int dd, int dm, Condition cc = AL)
    476476        {
    477477            emitDoublePrecisionInstruction(toARMWord(cc) | VABS_F64, dd, 0, dm);
    478478        }
    479479
    480         void vneg_f64_r(int dd, int dm, Condition cc = AL)
     480        void vneg_f64(int dd, int dm, Condition cc = AL)
    481481        {
    482482            emitDoublePrecisionInstruction(toARMWord(cc) | VNEG_F64, dd, 0, dm);
    483483        }
    484484
    485         void ldr_imm(int rd, ARMWord imm, Condition cc = AL)
     485        void ldrImmediate(int rd, ARMWord imm, Condition cc = AL)
    486486        {
    487487            m_buffer.putIntWithConstantInt(toARMWord(cc) | LoadUint32 | DataTransferUp | RN(ARMRegisters::pc) | RD(rd), imm, true);
    488488        }
    489489
    490         void ldr_un_imm(int rd, ARMWord imm, Condition cc = AL)
     490        void ldrUniqueImmediate(int rd, ARMWord imm, Condition cc = AL)
    491491        {
    492492            m_buffer.putIntWithConstantInt(toARMWord(cc) | LoadUint32 | DataTransferUp | RN(ARMRegisters::pc) | RD(rd), imm);
    493493        }
    494494
    495         void dtr_u(DataTransferTypeA transferType, int rd, int rb, ARMWord op2, Condition cc = AL)
     495        void dtrUp(DataTransferTypeA transferType, int rd, int rb, ARMWord op2, Condition cc = AL)
    496496        {
    497497            emitInstruction(toARMWord(cc) | transferType | DataTransferUp, rd, rb, op2);
    498498        }
    499499
    500         void dtr_ur(DataTransferTypeA transferType, int rd, int rb, int rm, Condition cc = AL)
     500        void dtrUpRegister(DataTransferTypeA transferType, int rd, int rb, int rm, Condition cc = AL)
    501501        {
    502502            emitInstruction(toARMWord(cc) | transferType | DataTransferUp | Op2IsRegisterArgument, rd, rb, rm);
    503503        }
    504504
    505         void dtr_d(DataTransferTypeA transferType, int rd, int rb, ARMWord op2, Condition cc = AL)
     505        void dtrDown(DataTransferTypeA transferType, int rd, int rb, ARMWord op2, Condition cc = AL)
    506506        {
    507507            emitInstruction(toARMWord(cc) | transferType, rd, rb, op2);
    508508        }
    509509
    510         void dtr_dr(DataTransferTypeA transferType, int rd, int rb, int rm, Condition cc = AL)
     510        void dtrDownRegister(DataTransferTypeA transferType, int rd, int rb, int rm, Condition cc = AL)
    511511        {
    512512            emitInstruction(toARMWord(cc) | transferType | Op2IsRegisterArgument, rd, rb, rm);
    513513        }
    514514
    515         void dtrh_u(DataTransferTypeB transferType, int rd, int rb, ARMWord op2, Condition cc = AL)
     515        void halfDtrUp(DataTransferTypeB transferType, int rd, int rb, ARMWord op2, Condition cc = AL)
    516516        {
    517517            emitInstruction(toARMWord(cc) | transferType | DataTransferUp, rd, rb, op2);
    518518        }
    519519
    520         void dtrh_ur(DataTransferTypeB transferType, int rd, int rn, int rm, Condition cc = AL)
     520        void halfDtrUpRegister(DataTransferTypeB transferType, int rd, int rn, int rm, Condition cc = AL)
    521521        {
    522522            emitInstruction(toARMWord(cc) | transferType | DataTransferUp, rd, rn, rm);
    523523        }
    524524
    525         void dtrh_d(DataTransferTypeB transferType, int rd, int rb, ARMWord op2, Condition cc = AL)
     525        void halfDtrDown(DataTransferTypeB transferType, int rd, int rb, ARMWord op2, Condition cc = AL)
    526526        {
    527527            emitInstruction(toARMWord(cc) | transferType, rd, rb, op2);
    528528        }
    529529
    530         void dtrh_dr(DataTransferTypeB transferType, int rd, int rn, int rm, Condition cc = AL)
     530        void halfDtrDownRegister(DataTransferTypeB transferType, int rd, int rn, int rm, Condition cc = AL)
    531531        {
    532532            emitInstruction(toARMWord(cc) | transferType, rd, rn, rm);
    533533        }
    534534
    535         void fdtr_u(DataTransferTypeFloat type, int rd, int rb, ARMWord op2, Condition cc = AL)
     535        void doubleDtrUp(DataTransferTypeFloat type, int rd, int rb, ARMWord op2, Condition cc = AL)
    536536        {
    537537            ASSERT(op2 <= 0xff && rd <= 15);
     
    540540        }
    541541
    542         void fdtr_d(DataTransferTypeFloat type, int rd, int rb, ARMWord op2, Condition cc = AL)
     542        void doubleDtrDown(DataTransferTypeFloat type, int rd, int rb, ARMWord op2, Condition cc = AL)
    543543        {
    544544            ASSERT(op2 <= 0xff && rd <= 15);
     
    547547        }
    548548
    549         void push_r(int reg, Condition cc = AL)
     549        void push(int reg, Condition cc = AL)
    550550        {
    551551            ASSERT(ARMWord(reg) <= 0xf);
     
    553553        }
    554554
    555         void pop_r(int reg, Condition cc = AL)
     555        void pop(int reg, Condition cc = AL)
    556556        {
    557557            ASSERT(ARMWord(reg) <= 0xf);
     
    559559        }
    560560
    561         inline void poke_r(int reg, Condition cc = AL)
    562         {
    563             dtr_d(StoreUint32, ARMRegisters::sp, 0, reg, cc);
    564         }
    565 
    566         inline void peek_r(int reg, Condition cc = AL)
    567         {
    568             dtr_u(LoadUint32, reg, ARMRegisters::sp, 0, cc);
    569         }
    570 
    571         void vmov_vfp64_r(int sm, int rt, int rt2, Condition cc = AL)
     561        inline void poke(int reg, Condition cc = AL)
     562        {
     563            dtrDown(StoreUint32, ARMRegisters::sp, 0, reg, cc);
     564        }
     565
     566        inline void peek(int reg, Condition cc = AL)
     567        {
     568            dtrUp(LoadUint32, reg, ARMRegisters::sp, 0, cc);
     569        }
     570
     571        void vmov_vfp64(int sm, int rt, int rt2, Condition cc = AL)
    572572        {
    573573            ASSERT(rt != rt2);
     
    575575        }
    576576
    577         void vmov_arm64_r(int rt, int rt2, int sm, Condition cc = AL)
     577        void vmov_arm64(int rt, int rt2, int sm, Condition cc = AL)
    578578        {
    579579            ASSERT(rt != rt2);
     
    581581        }
    582582
    583         void vmov_vfp32_r(int sn, int rt, Condition cc = AL)
     583        void vmov_vfp32(int sn, int rt, Condition cc = AL)
    584584        {
    585585            ASSERT(rt <= 15);
     
    587587        }
    588588
    589         void vmov_arm32_r(int rt, int sn, Condition cc = AL)
     589        void vmov_arm32(int rt, int sn, Condition cc = AL)
    590590        {
    591591            ASSERT(rt <= 15);
     
    593593        }
    594594
    595         void vcvt_f64_s32_r(int dd, int sm, Condition cc = AL)
     595        void vcvt_f64_s32(int dd, int sm, Condition cc = AL)
    596596        {
    597597            ASSERT(!(sm & 0x1)); // sm must be divisible by 2
     
    599599        }
    600600
    601         void vcvt_s32_f64_r(int sd, int dm, Condition cc = AL)
     601        void vcvt_s32_f64(int sd, int dm, Condition cc = AL)
    602602        {
    603603            ASSERT(!(sd & 0x1)); // sd must be divisible by 2
     
    605605        }
    606606
    607         void vcvt_u32_f64_r(int sd, int dm, Condition cc = AL)
     607        void vcvt_u32_f64(int sd, int dm, Condition cc = AL)
    608608        {
    609609            ASSERT(!(sd & 0x1)); // sd must be divisible by 2
     
    611611        }
    612612
    613         void vcvt_f64_f32_r(int dd, int sm, Condition cc = AL)
     613        void vcvt_f64_f32(int dd, int sm, Condition cc = AL)
    614614        {
    615615            ASSERT(dd <= 15 && sm <= 15);
     
    617617        }
    618618
    619         void vcvt_f32_f64_r(int dd, int sm, Condition cc = AL)
     619        void vcvt_f32_f64(int dd, int sm, Condition cc = AL)
    620620        {
    621621            ASSERT(dd <= 15 && sm <= 15);
     
    628628        }
    629629
    630         void clz_r(int rd, int rm, Condition cc = AL)
     630        void clz(int rd, int rm, Condition cc = AL)
    631631        {
    632632            m_buffer.putInt(toARMWord(cc) | CLZ | RD(rd) | RM(rm));
     
    675675        }
    676676
    677         static ARMWord lsl_r(int reg, int shiftReg)
     677        static ARMWord lslRegister(int reg, int shiftReg)
    678678        {
    679679            ASSERT(reg <= ARMRegisters::pc);
     
    682682        }
    683683
    684         static ARMWord lsr_r(int reg, int shiftReg)
     684        static ARMWord lsrRegister(int reg, int shiftReg)
    685685        {
    686686            ASSERT(reg <= ARMRegisters::pc);
     
    689689        }
    690690
    691         static ARMWord asr_r(int reg, int shiftReg)
     691        static ARMWord asrRegister(int reg, int shiftReg)
    692692        {
    693693            ASSERT(reg <= ARMRegisters::pc);
     
    743743        {
    744744            while (!m_buffer.isAligned(alignment))
    745                 mov_r(ARMRegisters::r0, ARMRegisters::r0);
     745                mov(ARMRegisters::r0, ARMRegisters::r0);
    746746
    747747            return label();
     
    752752            ensureSpace(sizeof(ARMWord), sizeof(ARMWord));
    753753            m_jumps.append(m_buffer.codeSize() | (useConstantPool & 0x1));
    754             ldr_un_imm(rd, InvalidBranchTarget, cc);
     754            ldrUniqueImmediate(rd, InvalidBranchTarget, cc);
    755755            return m_buffer.label();
    756756        }
     
    768768        void vmov(RegisterID rd1, RegisterID rd2, FPRegisterID rn)
    769769        {
    770             vmov_arm64_r(rd1, rd2, rn);
     770            vmov_arm64(rd1, rd2, rn);
    771771        }
    772772
    773773        void vmov(FPRegisterID rd, RegisterID rn1, RegisterID rn2)
    774774        {
    775             vmov_vfp64_r(rd, rn1, rn2);
     775            vmov_vfp64(rd, rn1, rn2);
    776776        }
    777777
  • trunk/Source/JavaScriptCore/assembler/MacroAssemblerARM.cpp

    r124930 r125541  
    7777
    7878    if (address.offset >= 0 && address.offset + 0x2 <= 0xff) {
    79         m_assembler.add_r(ARMRegisters::S0, address.base, op2);
    80         m_assembler.dtrh_u(ARMAssembler::LoadUint16, dest, ARMRegisters::S0, ARMAssembler::getOp2Half(address.offset));
    81         m_assembler.dtrh_u(ARMAssembler::LoadUint16, ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::getOp2Half(address.offset + 0x2));
     79        m_assembler.add(ARMRegisters::S0, address.base, op2);
     80        m_assembler.halfDtrUp(ARMAssembler::LoadUint16, dest, ARMRegisters::S0, ARMAssembler::getOp2Half(address.offset));
     81        m_assembler.halfDtrUp(ARMAssembler::LoadUint16, ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::getOp2Half(address.offset + 0x2));
    8282    } else if (address.offset < 0 && address.offset >= -0xff) {
    83         m_assembler.add_r(ARMRegisters::S0, address.base, op2);
    84         m_assembler.dtrh_d(ARMAssembler::LoadUint16, dest, ARMRegisters::S0, ARMAssembler::getOp2Half(-address.offset));
    85         m_assembler.dtrh_d(ARMAssembler::LoadUint16, ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::getOp2Half(-address.offset - 0x2));
     83        m_assembler.add(ARMRegisters::S0, address.base, op2);
     84        m_assembler.halfDtrDown(ARMAssembler::LoadUint16, dest, ARMRegisters::S0, ARMAssembler::getOp2Half(-address.offset));
     85        m_assembler.halfDtrDown(ARMAssembler::LoadUint16, ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::getOp2Half(-address.offset - 0x2));
    8686    } else {
    8787        m_assembler.moveImm(address.offset, ARMRegisters::S0);
    88         m_assembler.add_r(ARMRegisters::S0, ARMRegisters::S0, op2);
    89         m_assembler.dtrh_ur(ARMAssembler::LoadUint16, dest, address.base, ARMRegisters::S0);
    90         m_assembler.add_r(ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::Op2Immediate | 0x2);
    91         m_assembler.dtrh_ur(ARMAssembler::LoadUint16, ARMRegisters::S0, address.base, ARMRegisters::S0);
     88        m_assembler.add(ARMRegisters::S0, ARMRegisters::S0, op2);
     89        m_assembler.halfDtrUpRegister(ARMAssembler::LoadUint16, dest, address.base, ARMRegisters::S0);
     90        m_assembler.add(ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::Op2Immediate | 0x2);
     91        m_assembler.halfDtrUpRegister(ARMAssembler::LoadUint16, ARMRegisters::S0, address.base, ARMRegisters::S0);
    9292    }
    93     m_assembler.orr_r(dest, dest, m_assembler.lsl(ARMRegisters::S0, 16));
     93    m_assembler.orr(dest, dest, m_assembler.lsl(ARMRegisters::S0, 16));
    9494}
    9595#endif
  • trunk/Source/JavaScriptCore/assembler/MacroAssemblerARM.h

    r124930 r125541  
    8787    void add32(RegisterID src, RegisterID dest)
    8888    {
    89         m_assembler.adds_r(dest, dest, src);
     89        m_assembler.adds(dest, dest, src);
    9090    }
    9191
    9292    void add32(RegisterID op1, RegisterID op2, RegisterID dest)
    9393    {
    94         m_assembler.adds_r(dest, op1, op2);
     94        m_assembler.adds(dest, op1, op2);
    9595    }
    9696
     
    104104    void add32(TrustedImm32 imm, RegisterID dest)
    105105    {
    106         m_assembler.adds_r(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
     106        m_assembler.adds(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
    107107    }
    108108
     
    110110    {
    111111        move(TrustedImmPtr(src.m_ptr), ARMRegisters::S1);
    112         m_assembler.dtr_u(ARMAssembler::LoadUint32, ARMRegisters::S1, ARMRegisters::S1, 0);
     112        m_assembler.dtrUp(ARMAssembler::LoadUint32, ARMRegisters::S1, ARMRegisters::S1, 0);
    113113        add32(ARMRegisters::S1, dest);
    114114    }
     
    122122    void add32(RegisterID src, TrustedImm32 imm, RegisterID dest)
    123123    {
    124         m_assembler.adds_r(dest, src, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
     124        m_assembler.adds(dest, src, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
    125125    }
    126126
    127127    void and32(RegisterID src, RegisterID dest)
    128128    {
    129         m_assembler.ands_r(dest, dest, src);
     129        m_assembler.bitAnds(dest, dest, src);
    130130    }
    131131
    132132    void and32(RegisterID op1, RegisterID op2, RegisterID dest)
    133133    {
    134         m_assembler.ands_r(dest, op1, op2);
     134        m_assembler.bitAnds(dest, op1, op2);
    135135    }
    136136
     
    139139        ARMWord w = m_assembler.getImm(imm.m_value, ARMRegisters::S0, true);
    140140        if (w & ARMAssembler::Op2InvertedImmediate)
    141             m_assembler.bics_r(dest, dest, w & ~ARMAssembler::Op2InvertedImmediate);
     141            m_assembler.bics(dest, dest, w & ~ARMAssembler::Op2InvertedImmediate);
    142142        else
    143             m_assembler.ands_r(dest, dest, w);
     143            m_assembler.bitAnds(dest, dest, w);
    144144    }
    145145
     
    148148        ARMWord w = m_assembler.getImm(imm.m_value, ARMRegisters::S0, true);
    149149        if (w & ARMAssembler::Op2InvertedImmediate)
    150             m_assembler.bics_r(dest, src, w & ~ARMAssembler::Op2InvertedImmediate);
     150            m_assembler.bics(dest, src, w & ~ARMAssembler::Op2InvertedImmediate);
    151151        else
    152             m_assembler.ands_r(dest, src, w);
     152            m_assembler.bitAnds(dest, src, w);
    153153    }
    154154
     
    161161    {
    162162        ARMWord w = ARMAssembler::getOp2Byte(0x1f);
    163         m_assembler.and_r(ARMRegisters::S0, shiftAmount, w);
    164 
    165         m_assembler.movs_r(dest, m_assembler.lsl_r(src, ARMRegisters::S0));
     163        m_assembler.bitAnd(ARMRegisters::S0, shiftAmount, w);
     164
     165        m_assembler.movs(dest, m_assembler.lslRegister(src, ARMRegisters::S0));
    166166    }
    167167
    168168    void lshift32(TrustedImm32 imm, RegisterID dest)
    169169    {
    170         m_assembler.movs_r(dest, m_assembler.lsl(dest, imm.m_value & 0x1f));
     170        m_assembler.movs(dest, m_assembler.lsl(dest, imm.m_value & 0x1f));
    171171    }
    172172
    173173    void lshift32(RegisterID src, TrustedImm32 imm, RegisterID dest)
    174174    {
    175         m_assembler.movs_r(dest, m_assembler.lsl(src, imm.m_value & 0x1f));
     175        m_assembler.movs(dest, m_assembler.lsl(src, imm.m_value & 0x1f));
    176176    }
    177177
     
    189189            }
    190190        }
    191         m_assembler.muls_r(dest, op1, op2);
     191        m_assembler.muls(dest, op1, op2);
    192192    }
    193193
     
    200200    {
    201201        move(imm, ARMRegisters::S0);
    202         m_assembler.muls_r(dest, src, ARMRegisters::S0);
     202        m_assembler.muls(dest, src, ARMRegisters::S0);
    203203    }
    204204
     
    210210    void or32(RegisterID src, RegisterID dest)
    211211    {
    212         m_assembler.orrs_r(dest, dest, src);
     212        m_assembler.orrs(dest, dest, src);
    213213    }
    214214
    215215    void or32(TrustedImm32 imm, RegisterID dest)
    216216    {
    217         m_assembler.orrs_r(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
     217        m_assembler.orrs(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
    218218    }
    219219
    220220    void or32(TrustedImm32 imm, RegisterID src, RegisterID dest)
    221221    {
    222         m_assembler.orrs_r(dest, src, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
     222        m_assembler.orrs(dest, src, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
    223223    }
    224224
    225225    void or32(RegisterID op1, RegisterID op2, RegisterID dest)
    226226    {
    227         m_assembler.orrs_r(dest, op1, op2);
     227        m_assembler.orrs(dest, op1, op2);
    228228    }
    229229
     
    236236    {
    237237        ARMWord w = ARMAssembler::getOp2Byte(0x1f);
    238         m_assembler.and_r(ARMRegisters::S0, shiftAmount, w);
    239 
    240         m_assembler.movs_r(dest, m_assembler.asr_r(src, ARMRegisters::S0));
     238        m_assembler.bitAnd(ARMRegisters::S0, shiftAmount, w);
     239
     240        m_assembler.movs(dest, m_assembler.asrRegister(src, ARMRegisters::S0));
    241241    }
    242242
     
    248248    void rshift32(RegisterID src, TrustedImm32 imm, RegisterID dest)
    249249    {
    250         m_assembler.movs_r(dest, m_assembler.asr(src, imm.m_value & 0x1f));
     250        m_assembler.movs(dest, m_assembler.asr(src, imm.m_value & 0x1f));
    251251    }
    252252
     
    259259    {
    260260        ARMWord w = ARMAssembler::getOp2Byte(0x1f);
    261         m_assembler.and_r(ARMRegisters::S0, shiftAmount, w);
    262 
    263         m_assembler.movs_r(dest, m_assembler.lsr_r(src, ARMRegisters::S0));
     261        m_assembler.bitAnd(ARMRegisters::S0, shiftAmount, w);
     262
     263        m_assembler.movs(dest, m_assembler.lsrRegister(src, ARMRegisters::S0));
    264264    }
    265265
    266266    void urshift32(TrustedImm32 imm, RegisterID dest)
    267267    {
    268         m_assembler.movs_r(dest, m_assembler.lsr(dest, imm.m_value & 0x1f));
     268        m_assembler.movs(dest, m_assembler.lsr(dest, imm.m_value & 0x1f));
    269269    }
    270270   
    271271    void urshift32(RegisterID src, TrustedImm32 imm, RegisterID dest)
    272272    {
    273         m_assembler.movs_r(dest, m_assembler.lsr(src, imm.m_value & 0x1f));
     273        m_assembler.movs(dest, m_assembler.lsr(src, imm.m_value & 0x1f));
    274274    }
    275275
    276276    void sub32(RegisterID src, RegisterID dest)
    277277    {
    278         m_assembler.subs_r(dest, dest, src);
     278        m_assembler.subs(dest, dest, src);
    279279    }
    280280
    281281    void sub32(TrustedImm32 imm, RegisterID dest)
    282282    {
    283         m_assembler.subs_r(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
     283        m_assembler.subs(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
    284284    }
    285285
     
    299299    void sub32(RegisterID src, TrustedImm32 imm, RegisterID dest)
    300300    {
    301         m_assembler.subs_r(dest, src, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
     301        m_assembler.subs(dest, src, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
    302302    }
    303303
     
    315315    {
    316316        if (imm.m_value == -1)
    317             m_assembler.mvns_r(dest, dest);
     317            m_assembler.mvns(dest, dest);
    318318        else
    319319            m_assembler.eors_r(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
     
    323323    {
    324324        if (imm.m_value == -1)
    325             m_assembler.mvns_r(dest, src);
     325            m_assembler.mvns(dest, src);
    326326        else   
    327327            m_assembler.eors_r(dest, src, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
     
    331331    {
    332332#if WTF_ARM_ARCH_AT_LEAST(5)
    333         m_assembler.clz_r(dest, src);
     333        m_assembler.clz(dest, src);
    334334#else
    335335        UNUSED_PARAM(src);
     
    397397        ConvertibleLoadLabel result(this);
    398398        ASSERT(address.offset >= 0 && address.offset <= 255);
    399         m_assembler.dtr_u(ARMAssembler::LoadUint32, dest, address.base, address.offset);
     399        m_assembler.dtrUp(ARMAssembler::LoadUint32, dest, address.base, address.offset);
    400400        return result;
    401401    }
     
    404404    {
    405405        DataLabel32 dataLabel(this);
    406         m_assembler.ldr_un_imm(ARMRegisters::S0, 0);
    407         m_assembler.dtr_ur(ARMAssembler::LoadUint32, dest, address.base, ARMRegisters::S0);
     406        m_assembler.ldrUniqueImmediate(ARMRegisters::S0, 0);
     407        m_assembler.dtrUpRegister(ARMAssembler::LoadUint32, dest, address.base, ARMRegisters::S0);
    408408        return dataLabel;
    409409    }
     
    419419        ASSERT(isCompactPtrAlignedAddressOffset(address.offset));
    420420        if (address.offset >= 0)
    421             m_assembler.dtr_u(ARMAssembler::LoadUint32, dest, address.base, address.offset);
     421            m_assembler.dtrUp(ARMAssembler::LoadUint32, dest, address.base, address.offset);
    422422        else
    423             m_assembler.dtr_d(ARMAssembler::LoadUint32, dest, address.base, address.offset);
     423            m_assembler.dtrDown(ARMAssembler::LoadUint32, dest, address.base, address.offset);
    424424        return dataLabel;
    425425    }
     
    428428    {
    429429        DataLabel32 dataLabel(this);
    430         m_assembler.ldr_un_imm(ARMRegisters::S0, 0);
    431         m_assembler.dtr_ur(ARMAssembler::StoreUint32, src, address.base, ARMRegisters::S0);
     430        m_assembler.ldrUniqueImmediate(ARMRegisters::S0, 0);
     431        m_assembler.dtrUpRegister(ARMAssembler::StoreUint32, src, address.base, ARMRegisters::S0);
    432432        return dataLabel;
    433433    }
     
    467467    void store32(RegisterID src, void* address)
    468468    {
    469         m_assembler.ldr_un_imm(ARMRegisters::S0, reinterpret_cast<ARMWord>(address));
    470         m_assembler.dtr_u(ARMAssembler::StoreUint32, src, ARMRegisters::S0, 0);
     469        m_assembler.ldrUniqueImmediate(ARMRegisters::S0, reinterpret_cast<ARMWord>(address));
     470        m_assembler.dtrUp(ARMAssembler::StoreUint32, src, ARMRegisters::S0, 0);
    471471    }
    472472
    473473    void store32(TrustedImm32 imm, void* address)
    474474    {
    475         m_assembler.ldr_un_imm(ARMRegisters::S0, reinterpret_cast<ARMWord>(address));
     475        m_assembler.ldrUniqueImmediate(ARMRegisters::S0, reinterpret_cast<ARMWord>(address));
    476476        m_assembler.moveImm(imm.m_value, ARMRegisters::S1);
    477         m_assembler.dtr_u(ARMAssembler::StoreUint32, ARMRegisters::S1, ARMRegisters::S0, 0);
     477        m_assembler.dtrUp(ARMAssembler::StoreUint32, ARMRegisters::S1, ARMRegisters::S0, 0);
    478478    }
    479479
    480480    void pop(RegisterID dest)
    481481    {
    482         m_assembler.pop_r(dest);
     482        m_assembler.pop(dest);
    483483    }
    484484
    485485    void push(RegisterID src)
    486486    {
    487         m_assembler.push_r(src);
     487        m_assembler.push(src);
    488488    }
    489489
     
    508508    {
    509509        if (src != dest)
    510             m_assembler.mov_r(dest, src);
     510            m_assembler.mov(dest, src);
    511511    }
    512512
     
    518518    void swap(RegisterID reg1, RegisterID reg2)
    519519    {
    520         m_assembler.mov_r(ARMRegisters::S0, reg1);
    521         m_assembler.mov_r(reg1, reg2);
    522         m_assembler.mov_r(reg2, ARMRegisters::S0);
     520        m_assembler.mov(ARMRegisters::S0, reg1);
     521        m_assembler.mov(reg1, reg2);
     522        m_assembler.mov(reg2, ARMRegisters::S0);
    523523    }
    524524
     
    550550    Jump branch32(RelationalCondition cond, RegisterID left, RegisterID right, int useConstantPool = 0)
    551551    {
    552         m_assembler.cmp_r(left, right);
     552        m_assembler.cmp(left, right);
    553553        return Jump(m_assembler.jmp(ARMCondition(cond), useConstantPool));
    554554    }
     
    558558        ARMWord tmp = (right.m_value == 0x80000000) ? ARMAssembler::InvalidImmediate : m_assembler.getOp2(-right.m_value);
    559559        if (tmp != ARMAssembler::InvalidImmediate)
    560             m_assembler.cmn_r(left, tmp);
     560            m_assembler.cmn(left, tmp);
    561561        else
    562             m_assembler.cmp_r(left, m_assembler.getImm(right.m_value, ARMRegisters::S0));
     562            m_assembler.cmp(left, m_assembler.getImm(right.m_value, ARMRegisters::S0));
    563563        return Jump(m_assembler.jmp(ARMCondition(cond), useConstantPool));
    564564    }
     
    610610    {
    611611        ASSERT((cond == Zero) || (cond == NonZero));
    612         m_assembler.tst_r(reg, mask);
     612        m_assembler.tst(reg, mask);
    613613        return Jump(m_assembler.jmp(ARMCondition(cond)));
    614614    }
     
    619619        ARMWord w = m_assembler.getImm(mask.m_value, ARMRegisters::S0, true);
    620620        if (w & ARMAssembler::Op2InvertedImmediate)
    621             m_assembler.bics_r(ARMRegisters::S0, reg, w & ~ARMAssembler::Op2InvertedImmediate);
     621            m_assembler.bics(ARMRegisters::S0, reg, w & ~ARMAssembler::Op2InvertedImmediate);
    622622        else
    623             m_assembler.tst_r(reg, w);
     623            m_assembler.tst(reg, w);
    624624        return Jump(m_assembler.jmp(ARMCondition(cond)));
    625625    }
     
    706706            }
    707707        }
    708         m_assembler.mull_r(ARMRegisters::S1, dest, op1, op2);
    709         m_assembler.cmp_r(ARMRegisters::S1, m_assembler.asr(dest, 31));
     708        m_assembler.mull(ARMRegisters::S1, dest, op1, op2);
     709        m_assembler.cmp(ARMRegisters::S1, m_assembler.asr(dest, 31));
    710710    }
    711711
     
    764764    {
    765765        ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
    766         m_assembler.subs_r(dest, op1, op2);
     766        m_assembler.subs(dest, op1, op2);
    767767        return Jump(m_assembler.jmp(ARMCondition(cond)));
    768768    }
     
    810810    void compare32(RelationalCondition cond, RegisterID left, RegisterID right, RegisterID dest)
    811811    {
    812         m_assembler.cmp_r(left, right);
    813         m_assembler.mov_r(dest, ARMAssembler::getOp2Byte(0));
    814         m_assembler.mov_r(dest, ARMAssembler::getOp2Byte(1), ARMCondition(cond));
     812        m_assembler.cmp(left, right);
     813        m_assembler.mov(dest, ARMAssembler::getOp2Byte(0));
     814        m_assembler.mov(dest, ARMAssembler::getOp2Byte(1), ARMCondition(cond));
    815815    }
    816816
    817817    void compare32(RelationalCondition cond, RegisterID left, TrustedImm32 right, RegisterID dest)
    818818    {
    819         m_assembler.cmp_r(left, m_assembler.getImm(right.m_value, ARMRegisters::S0));
    820         m_assembler.mov_r(dest, ARMAssembler::getOp2Byte(0));
    821         m_assembler.mov_r(dest, ARMAssembler::getOp2Byte(1), ARMCondition(cond));
     819        m_assembler.cmp(left, m_assembler.getImm(right.m_value, ARMRegisters::S0));
     820        m_assembler.mov(dest, ARMAssembler::getOp2Byte(0));
     821        m_assembler.mov(dest, ARMAssembler::getOp2Byte(1), ARMCondition(cond));
    822822    }
    823823
     
    831831    {
    832832        if (mask.m_value == -1)
    833             m_assembler.cmp_r(0, reg);
     833            m_assembler.cmp(0, reg);
    834834        else
    835             m_assembler.tst_r(reg, m_assembler.getImm(mask.m_value, ARMRegisters::S0));
    836         m_assembler.mov_r(dest, ARMAssembler::getOp2Byte(0));
    837         m_assembler.mov_r(dest, ARMAssembler::getOp2Byte(1), ARMCondition(cond));
     835            m_assembler.tst(reg, m_assembler.getImm(mask.m_value, ARMRegisters::S0));
     836        m_assembler.mov(dest, ARMAssembler::getOp2Byte(0));
     837        m_assembler.mov(dest, ARMAssembler::getOp2Byte(1), ARMCondition(cond));
    838838    }
    839839
     
    852852    void add32(TrustedImm32 imm, RegisterID src, RegisterID dest)
    853853    {
    854         m_assembler.add_r(dest, src, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
     854        m_assembler.add(dest, src, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
    855855    }
    856856
    857857    void add32(TrustedImm32 imm, AbsoluteAddress address)
    858858    {
    859         m_assembler.ldr_un_imm(ARMRegisters::S1, reinterpret_cast<ARMWord>(address.m_ptr));
    860         m_assembler.dtr_u(ARMAssembler::LoadUint32, ARMRegisters::S1, ARMRegisters::S1, 0);
     859        m_assembler.ldrUniqueImmediate(ARMRegisters::S1, reinterpret_cast<ARMWord>(address.m_ptr));
     860        m_assembler.dtrUp(ARMAssembler::LoadUint32, ARMRegisters::S1, ARMRegisters::S1, 0);
    861861        add32(imm, ARMRegisters::S1);
    862         m_assembler.ldr_un_imm(ARMRegisters::S0, reinterpret_cast<ARMWord>(address.m_ptr));
    863         m_assembler.dtr_u(ARMAssembler::StoreUint32, ARMRegisters::S1, ARMRegisters::S0, 0);
     862        m_assembler.ldrUniqueImmediate(ARMRegisters::S0, reinterpret_cast<ARMWord>(address.m_ptr));
     863        m_assembler.dtrUp(ARMAssembler::StoreUint32, ARMRegisters::S1, ARMRegisters::S0, 0);
    864864    }
    865865
    866866    void sub32(TrustedImm32 imm, AbsoluteAddress address)
    867867    {
    868         m_assembler.ldr_un_imm(ARMRegisters::S1, reinterpret_cast<ARMWord>(address.m_ptr));
    869         m_assembler.dtr_u(ARMAssembler::LoadUint32, ARMRegisters::S1, ARMRegisters::S1, 0);
     868        m_assembler.ldrUniqueImmediate(ARMRegisters::S1, reinterpret_cast<ARMWord>(address.m_ptr));
     869        m_assembler.dtrUp(ARMAssembler::LoadUint32, ARMRegisters::S1, ARMRegisters::S1, 0);
    870870        sub32(imm, ARMRegisters::S1);
    871         m_assembler.ldr_un_imm(ARMRegisters::S0, reinterpret_cast<ARMWord>(address.m_ptr));
    872         m_assembler.dtr_u(ARMAssembler::StoreUint32, ARMRegisters::S1, ARMRegisters::S0, 0);
     871        m_assembler.ldrUniqueImmediate(ARMRegisters::S0, reinterpret_cast<ARMWord>(address.m_ptr));
     872        m_assembler.dtrUp(ARMAssembler::StoreUint32, ARMRegisters::S1, ARMRegisters::S0, 0);
    873873    }
    874874
    875875    void load32(const void* address, RegisterID dest)
    876876    {
    877         m_assembler.ldr_un_imm(ARMRegisters::S0, reinterpret_cast<ARMWord>(address));
    878         m_assembler.dtr_u(ARMAssembler::LoadUint32, dest, ARMRegisters::S0, 0);
     877        m_assembler.ldrUniqueImmediate(ARMRegisters::S0, reinterpret_cast<ARMWord>(address));
     878        m_assembler.dtrUp(ARMAssembler::LoadUint32, dest, ARMRegisters::S0, 0);
    879879    }
    880880
     
    894894    {
    895895        ASSERT(scale >= 0 && scale <= 31);
    896         m_assembler.add_r(ARMRegisters::pc, ARMRegisters::pc, m_assembler.lsl(index, scale));
     896        m_assembler.add(ARMRegisters::pc, ARMRegisters::pc, m_assembler.lsl(index, scale));
    897897
    898898        // NOP the default prefetching
    899         m_assembler.mov_r(ARMRegisters::r0, ARMRegisters::r0);
     899        m_assembler.mov(ARMRegisters::r0, ARMRegisters::r0);
    900900    }
    901901
     
    920920    {
    921921        DataLabelPtr dataLabel(this);
    922         m_assembler.ldr_un_imm(dest, reinterpret_cast<ARMWord>(initialValue.m_value));
     922        m_assembler.ldrUniqueImmediate(dest, reinterpret_cast<ARMWord>(initialValue.m_value));
    923923        return dataLabel;
    924924    }
     
    986986    {
    987987        move(TrustedImm32(reinterpret_cast<ARMWord>(address)), ARMRegisters::S0);
    988         m_assembler.fdtr_u(ARMAssembler::LoadDouble, dest, ARMRegisters::S0, 0);
     988        m_assembler.doubleDtrUp(ARMAssembler::LoadDouble, dest, ARMRegisters::S0, 0);
    989989    }
    990990
     
    10131013    {
    10141014        if (src != dest)
    1015             m_assembler.vmov_f64_r(dest, src);
     1015            m_assembler.vmov_f64(dest, src);
    10161016    }
    10171017
    10181018    void addDouble(FPRegisterID src, FPRegisterID dest)
    10191019    {
    1020         m_assembler.vadd_f64_r(dest, dest, src);
     1020        m_assembler.vadd_f64(dest, dest, src);
    10211021    }
    10221022
    10231023    void addDouble(FPRegisterID op1, FPRegisterID op2, FPRegisterID dest)
    10241024    {
    1025         m_assembler.vadd_f64_r(dest, op1, op2);
     1025        m_assembler.vadd_f64(dest, op1, op2);
    10261026    }
    10271027
     
    10401040    void divDouble(FPRegisterID src, FPRegisterID dest)
    10411041    {
    1042         m_assembler.vdiv_f64_r(dest, dest, src);
     1042        m_assembler.vdiv_f64(dest, dest, src);
    10431043    }
    10441044
    10451045    void divDouble(FPRegisterID op1, FPRegisterID op2, FPRegisterID dest)
    10461046    {
    1047         m_assembler.vdiv_f64_r(dest, op1, op2);
     1047        m_assembler.vdiv_f64(dest, op1, op2);
    10481048    }
    10491049
     
    10571057    void subDouble(FPRegisterID src, FPRegisterID dest)
    10581058    {
    1059         m_assembler.vsub_f64_r(dest, dest, src);
     1059        m_assembler.vsub_f64(dest, dest, src);
    10601060    }
    10611061
    10621062    void subDouble(FPRegisterID op1, FPRegisterID op2, FPRegisterID dest)
    10631063    {
    1064         m_assembler.vsub_f64_r(dest, op1, op2);
     1064        m_assembler.vsub_f64(dest, op1, op2);
    10651065    }
    10661066
     
    10731073    void mulDouble(FPRegisterID src, FPRegisterID dest)
    10741074    {
    1075         m_assembler.vmul_f64_r(dest, dest, src);
     1075        m_assembler.vmul_f64(dest, dest, src);
    10761076    }
    10771077
     
    10841084    void mulDouble(FPRegisterID op1, FPRegisterID op2, FPRegisterID dest)
    10851085    {
    1086         m_assembler.vmul_f64_r(dest, op1, op2);
     1086        m_assembler.vmul_f64(dest, op1, op2);
    10871087    }
    10881088
    10891089    void sqrtDouble(FPRegisterID src, FPRegisterID dest)
    10901090    {
    1091         m_assembler.vsqrt_f64_r(dest, src);
     1091        m_assembler.vsqrt_f64(dest, src);
    10921092    }
    10931093   
    10941094    void absDouble(FPRegisterID src, FPRegisterID dest)
    10951095    {
    1096         m_assembler.vabs_f64_r(dest, src);
     1096        m_assembler.vabs_f64(dest, src);
    10971097    }
    10981098
    10991099    void negateDouble(FPRegisterID src, FPRegisterID dest)
    11001100    {
    1101         m_assembler.vneg_f64_r(dest, src);
     1101        m_assembler.vneg_f64(dest, src);
    11021102    }
    11031103
    11041104    void convertInt32ToDouble(RegisterID src, FPRegisterID dest)
    11051105    {
    1106         m_assembler.vmov_vfp32_r(dest << 1, src);
    1107         m_assembler.vcvt_f64_s32_r(dest, dest << 1);
     1106        m_assembler.vmov_vfp32(dest << 1, src);
     1107        m_assembler.vcvt_f64_s32(dest, dest << 1);
    11081108    }
    11091109
     
    11231123    void convertFloatToDouble(FPRegisterID src, FPRegisterID dst)
    11241124    {
    1125         m_assembler.vcvt_f64_f32_r(dst, src);
     1125        m_assembler.vcvt_f64_f32(dst, src);
    11261126    }
    11271127
    11281128    void convertDoubleToFloat(FPRegisterID src, FPRegisterID dst)
    11291129    {
    1130         m_assembler.vcvt_f32_f64_r(dst, src);
     1130        m_assembler.vcvt_f32_f64(dst, src);
    11311131    }
    11321132
    11331133    Jump branchDouble(DoubleCondition cond, FPRegisterID left, FPRegisterID right)
    11341134    {
    1135         m_assembler.vcmp_f64_r(left, right);
     1135        m_assembler.vcmp_f64(left, right);
    11361136        m_assembler.vmrs_apsr();
    11371137        if (cond & DoubleConditionBitSpecial)
    1138             m_assembler.cmp_r(ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::VS);
     1138            m_assembler.cmp(ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::VS);
    11391139        return Jump(m_assembler.jmp(static_cast<ARMAssembler::Condition>(cond & ~DoubleConditionMask)));
    11401140    }
     
    11491149        truncateDoubleToInt32(src, dest);
    11501150
    1151         m_assembler.add_r(ARMRegisters::S0, dest, ARMAssembler::getOp2Byte(1));
    1152         m_assembler.bic_r(ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::getOp2Byte(1));
     1151        m_assembler.add(ARMRegisters::S0, dest, ARMAssembler::getOp2Byte(1));
     1152        m_assembler.bic(ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::getOp2Byte(1));
    11531153
    11541154        ARMWord w = ARMAssembler::getOp2(0x80000000);
    11551155        ASSERT(w != ARMAssembler::InvalidImmediate);
    1156         m_assembler.cmp_r(ARMRegisters::S0, w);
     1156        m_assembler.cmp(ARMRegisters::S0, w);
    11571157        return Jump(m_assembler.jmp(branchType == BranchIfTruncateFailed ? ARMAssembler::EQ : ARMAssembler::NE));
    11581158    }
     
    11621162        truncateDoubleToUint32(src, dest);
    11631163
    1164         m_assembler.add_r(ARMRegisters::S0, dest, ARMAssembler::getOp2Byte(1));
    1165         m_assembler.bic_r(ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::getOp2Byte(1));
    1166 
    1167         m_assembler.cmp_r(ARMRegisters::S0, ARMAssembler::getOp2Byte(0));
     1164        m_assembler.add(ARMRegisters::S0, dest, ARMAssembler::getOp2Byte(1));
     1165        m_assembler.bic(ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::getOp2Byte(1));
     1166
     1167        m_assembler.cmp(ARMRegisters::S0, ARMAssembler::getOp2Byte(0));
    11681168        return Jump(m_assembler.jmp(branchType == BranchIfTruncateFailed ? ARMAssembler::EQ : ARMAssembler::NE));
    11691169    }
     
    11721172    void truncateDoubleToInt32(FPRegisterID src, RegisterID dest)
    11731173    {
    1174         m_assembler.vcvt_s32_f64_r(ARMRegisters::SD0 << 1, src);
    1175         m_assembler.vmov_arm32_r(dest, ARMRegisters::SD0 << 1);
     1174        m_assembler.vcvt_s32_f64(ARMRegisters::SD0 << 1, src);
     1175        m_assembler.vmov_arm32(dest, ARMRegisters::SD0 << 1);
    11761176    }
    11771177
    11781178    void truncateDoubleToUint32(FPRegisterID src, RegisterID dest)
    11791179    {
    1180         m_assembler.vcvt_u32_f64_r(ARMRegisters::SD0 << 1, src);
    1181         m_assembler.vmov_arm32_r(dest, ARMRegisters::SD0 << 1);
     1180        m_assembler.vcvt_u32_f64(ARMRegisters::SD0 << 1, src);
     1181        m_assembler.vmov_arm32(dest, ARMRegisters::SD0 << 1);
    11821182    }
    11831183
     
    11881188    void branchConvertDoubleToInt32(FPRegisterID src, RegisterID dest, JumpList& failureCases, FPRegisterID fpTemp)
    11891189    {
    1190         m_assembler.vcvt_s32_f64_r(ARMRegisters::SD0 << 1, src);
    1191         m_assembler.vmov_arm32_r(dest, ARMRegisters::SD0 << 1);
     1190        m_assembler.vcvt_s32_f64(ARMRegisters::SD0 << 1, src);
     1191        m_assembler.vmov_arm32(dest, ARMRegisters::SD0 << 1);
    11921192
    11931193        // Convert the integer result back to float & compare to the original value - if not equal or unordered (NaN) then jump.
    1194         m_assembler.vcvt_f64_s32_r(ARMRegisters::SD0, ARMRegisters::SD0 << 1);
     1194        m_assembler.vcvt_f64_s32(ARMRegisters::SD0, ARMRegisters::SD0 << 1);
    11951195        failureCases.append(branchDouble(DoubleNotEqualOrUnordered, src, ARMRegisters::SD0));
    11961196
     
    12011201    Jump branchDoubleNonZero(FPRegisterID reg, FPRegisterID scratch)
    12021202    {
    1203         m_assembler.mov_r(ARMRegisters::S0, ARMAssembler::getOp2Byte(0));
     1203        m_assembler.mov(ARMRegisters::S0, ARMAssembler::getOp2Byte(0));
    12041204        convertInt32ToDouble(ARMRegisters::S0, scratch);
    12051205        return branchDouble(DoubleNotEqual, reg, scratch);
     
    12081208    Jump branchDoubleZeroOrNaN(FPRegisterID reg, FPRegisterID scratch)
    12091209    {
    1210         m_assembler.mov_r(ARMRegisters::S0, ARMAssembler::getOp2Byte(0));
     1210        m_assembler.mov(ARMRegisters::S0, ARMAssembler::getOp2Byte(0));
    12111211        convertInt32ToDouble(ARMRegisters::S0, scratch);
    12121212        return branchDouble(DoubleEqualOrUnordered, reg, scratch);
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