Changeset 125541 in webkit
- Timestamp:
- Aug 14, 2012 4:28:25 AM (12 years ago)
- Location:
- trunk/Source/JavaScriptCore
- Files:
-
- 5 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/Source/JavaScriptCore/ChangeLog
r125452 r125541 1 2012-08-14 Gabor Ballabas <gaborb@inf.u-szeged.hu> 2 3 Rename functions in the ARM port of DFG-JIT for better code readability. 4 https://bugs.webkit.org/show_bug.cgi?id=93609 5 6 Reviewed by Zoltan Herczeg. 7 8 Rename functions in the ARM port of DFG-JIT for better code 9 readability, and for following the WebKit coding style 10 wherever it is possible. 11 12 * assembler/ARMAssembler.cpp: 13 (JSC::ARMAssembler::genInt): 14 (JSC::ARMAssembler::getImm): 15 (JSC::ARMAssembler::moveImm): 16 (JSC::ARMAssembler::encodeComplexImm): 17 (JSC::ARMAssembler::dataTransfer32): 18 (JSC::ARMAssembler::baseIndexTransfer32): 19 (JSC::ARMAssembler::dataTransfer16): 20 (JSC::ARMAssembler::baseIndexTransfer16): 21 (JSC::ARMAssembler::dataTransferFloat): 22 (JSC::ARMAssembler::baseIndexTransferFloat): 23 * assembler/ARMAssembler.h: 24 (JSC::ARMAssembler::bitAnd): 25 (JSC::ARMAssembler::bitAnds): 26 (JSC::ARMAssembler::eor): 27 (JSC::ARMAssembler::eors): 28 (JSC::ARMAssembler::sub): 29 (JSC::ARMAssembler::subs): 30 (JSC::ARMAssembler::rsb): 31 (JSC::ARMAssembler::rsbs): 32 (JSC::ARMAssembler::add): 33 (JSC::ARMAssembler::adds): 34 (JSC::ARMAssembler::adc): 35 (JSC::ARMAssembler::adcs): 36 (JSC::ARMAssembler::sbc): 37 (JSC::ARMAssembler::sbcs): 38 (JSC::ARMAssembler::rsc): 39 (JSC::ARMAssembler::rscs): 40 (JSC::ARMAssembler::tst): 41 (JSC::ARMAssembler::teq): 42 (JSC::ARMAssembler::cmp): 43 (JSC::ARMAssembler::cmn): 44 (JSC::ARMAssembler::orr): 45 (JSC::ARMAssembler::orrs): 46 (JSC::ARMAssembler::mov): 47 (JSC::ARMAssembler::movw): 48 (JSC::ARMAssembler::movt): 49 (JSC::ARMAssembler::movs): 50 (JSC::ARMAssembler::bic): 51 (JSC::ARMAssembler::bics): 52 (JSC::ARMAssembler::mvn): 53 (JSC::ARMAssembler::mvns): 54 (JSC::ARMAssembler::mul): 55 (JSC::ARMAssembler::muls): 56 (JSC::ARMAssembler::mull): 57 (JSC::ARMAssembler::vmov_f64): 58 (JSC::ARMAssembler::vadd_f64): 59 (JSC::ARMAssembler::vdiv_f64): 60 (JSC::ARMAssembler::vsub_f64): 61 (JSC::ARMAssembler::vmul_f64): 62 (JSC::ARMAssembler::vcmp_f64): 63 (JSC::ARMAssembler::vsqrt_f64): 64 (JSC::ARMAssembler::vabs_f64): 65 (JSC::ARMAssembler::vneg_f64): 66 (JSC::ARMAssembler::ldrImmediate): 67 (JSC::ARMAssembler::ldrUniqueImmediate): 68 (JSC::ARMAssembler::dtrUp): 69 (JSC::ARMAssembler::dtrUpRegister): 70 (JSC::ARMAssembler::dtrDown): 71 (JSC::ARMAssembler::dtrDownRegister): 72 (JSC::ARMAssembler::halfDtrUp): 73 (JSC::ARMAssembler::halfDtrUpRegister): 74 (JSC::ARMAssembler::halfDtrDown): 75 (JSC::ARMAssembler::halfDtrDownRegister): 76 (JSC::ARMAssembler::doubleDtrUp): 77 (JSC::ARMAssembler::doubleDtrDown): 78 (JSC::ARMAssembler::push): 79 (JSC::ARMAssembler::pop): 80 (JSC::ARMAssembler::poke): 81 (JSC::ARMAssembler::peek): 82 (JSC::ARMAssembler::vmov_vfp64): 83 (JSC::ARMAssembler::vmov_arm64): 84 (JSC::ARMAssembler::vmov_vfp32): 85 (JSC::ARMAssembler::vmov_arm32): 86 (JSC::ARMAssembler::vcvt_f64_s32): 87 (JSC::ARMAssembler::vcvt_s32_f64): 88 (JSC::ARMAssembler::vcvt_u32_f64): 89 (JSC::ARMAssembler::vcvt_f64_f32): 90 (JSC::ARMAssembler::vcvt_f32_f64): 91 (JSC::ARMAssembler::clz): 92 (JSC::ARMAssembler::lslRegister): 93 (JSC::ARMAssembler::lsrRegister): 94 (JSC::ARMAssembler::asrRegister): 95 (JSC::ARMAssembler::align): 96 (JSC::ARMAssembler::loadBranchTarget): 97 (JSC::ARMAssembler::vmov): 98 * assembler/MacroAssemblerARM.cpp: 99 (JSC::MacroAssemblerARM::load32WithUnalignedHalfWords): 100 * assembler/MacroAssemblerARM.h: 101 (JSC::MacroAssemblerARM::add32): 102 (JSC::MacroAssemblerARM::and32): 103 (JSC::MacroAssemblerARM::lshift32): 104 (JSC::MacroAssemblerARM::mul32): 105 (JSC::MacroAssemblerARM::or32): 106 (JSC::MacroAssemblerARM::rshift32): 107 (JSC::MacroAssemblerARM::urshift32): 108 (JSC::MacroAssemblerARM::sub32): 109 (JSC::MacroAssemblerARM::xor32): 110 (JSC::MacroAssemblerARM::countLeadingZeros32): 111 (JSC::MacroAssemblerARM::convertibleLoadPtr): 112 (JSC::MacroAssemblerARM::load32WithAddressOffsetPatch): 113 (JSC::MacroAssemblerARM::load32WithCompactAddressOffsetPatch): 114 (JSC::MacroAssemblerARM::store32WithAddressOffsetPatch): 115 (JSC::MacroAssemblerARM::store32): 116 (JSC::MacroAssemblerARM::pop): 117 (JSC::MacroAssemblerARM::push): 118 (JSC::MacroAssemblerARM::move): 119 (JSC::MacroAssemblerARM::swap): 120 (JSC::MacroAssemblerARM::branch32): 121 (JSC::MacroAssemblerARM::branchTest32): 122 (JSC::MacroAssemblerARM::mull32): 123 (JSC::MacroAssemblerARM::branchSub32): 124 (JSC::MacroAssemblerARM::compare32): 125 (JSC::MacroAssemblerARM::test32): 126 (JSC::MacroAssemblerARM::load32): 127 (JSC::MacroAssemblerARM::relativeTableJump): 128 (JSC::MacroAssemblerARM::moveWithPatch): 129 (JSC::MacroAssemblerARM::loadDouble): 130 (JSC::MacroAssemblerARM::moveDouble): 131 (JSC::MacroAssemblerARM::addDouble): 132 (JSC::MacroAssemblerARM::divDouble): 133 (JSC::MacroAssemblerARM::subDouble): 134 (JSC::MacroAssemblerARM::mulDouble): 135 (JSC::MacroAssemblerARM::sqrtDouble): 136 (JSC::MacroAssemblerARM::absDouble): 137 (JSC::MacroAssemblerARM::negateDouble): 138 (JSC::MacroAssemblerARM::convertInt32ToDouble): 139 (JSC::MacroAssemblerARM::convertFloatToDouble): 140 (JSC::MacroAssemblerARM::convertDoubleToFloat): 141 (JSC::MacroAssemblerARM::branchDouble): 142 (JSC::MacroAssemblerARM::branchTruncateDoubleToInt32): 143 (JSC::MacroAssemblerARM::branchTruncateDoubleToUint32): 144 (JSC::MacroAssemblerARM::truncateDoubleToInt32): 145 (JSC::MacroAssemblerARM::truncateDoubleToUint32): 146 (JSC::MacroAssemblerARM::branchConvertDoubleToInt32): 147 (JSC::MacroAssemblerARM::branchDoubleNonZero): 148 (JSC::MacroAssemblerARM::branchDoubleZeroOrNaN): 149 1 150 2012-08-13 Simon Hausmann <simon.hausmann@nokia.com> 2 151 -
trunk/Source/JavaScriptCore/assembler/ARMAssembler.cpp
r124930 r125541 188 188 189 189 if (positive) { 190 mov _r(reg, imm1);191 orr _r(reg, reg, imm2);190 mov(reg, imm1); 191 orr(reg, reg, imm2); 192 192 } else { 193 mvn _r(reg, imm1);194 bic _r(reg, reg, imm2);193 mvn(reg, imm1); 194 bic(reg, reg, imm2); 195 195 } 196 196 … … 211 211 if (invert) 212 212 return tmp | Op2InvertedImmediate; 213 mvn _r(tmpReg, tmp);213 mvn(tmpReg, tmp); 214 214 return tmpReg; 215 215 } … … 225 225 tmp = getOp2(imm); 226 226 if (tmp != InvalidImmediate) { 227 mov _r(dest, tmp);227 mov(dest, tmp); 228 228 return; 229 229 } … … 231 231 tmp = getOp2(~imm); 232 232 if (tmp != InvalidImmediate) { 233 mvn _r(dest, tmp);233 mvn(dest, tmp); 234 234 return; 235 235 } … … 243 243 ARMWord tmp = getImm16Op2(imm); 244 244 if (tmp != InvalidImmediate) { 245 movw _r(dest, tmp);245 movw(dest, tmp); 246 246 return dest; 247 247 } 248 movw _r(dest, getImm16Op2(imm & 0xffff));249 movt _r(dest, getImm16Op2(imm >> 16));248 movw(dest, getImm16Op2(imm & 0xffff)); 249 movt(dest, getImm16Op2(imm >> 16)); 250 250 return dest; 251 251 #else … … 256 256 return dest; 257 257 258 ldr _imm(dest, imm);258 ldrImmediate(dest, imm); 259 259 return dest; 260 260 #endif … … 267 267 if (offset >= 0) { 268 268 if (offset <= 0xfff) 269 dtr _u(transferType, srcDst, base, offset);269 dtrUp(transferType, srcDst, base, offset); 270 270 else if (offset <= 0xfffff) { 271 add _r(ARMRegisters::S0, base, Op2Immediate | (offset >> 12) | (10 << 8));272 dtr _u(transferType, srcDst, ARMRegisters::S0, (offset & 0xfff));271 add(ARMRegisters::S0, base, Op2Immediate | (offset >> 12) | (10 << 8)); 272 dtrUp(transferType, srcDst, ARMRegisters::S0, (offset & 0xfff)); 273 273 } else { 274 274 moveImm(offset, ARMRegisters::S0); 275 dtr _ur(transferType, srcDst, base, ARMRegisters::S0);275 dtrUpRegister(transferType, srcDst, base, ARMRegisters::S0); 276 276 } 277 277 } else { 278 278 if (offset >= -0xfff) 279 dtr _d(transferType, srcDst, base, -offset);279 dtrDown(transferType, srcDst, base, -offset); 280 280 else if (offset >= -0xfffff) { 281 sub _r(ARMRegisters::S0, base, Op2Immediate | (-offset >> 12) | (10 << 8));282 dtr _d(transferType, srcDst, ARMRegisters::S0, (-offset & 0xfff));281 sub(ARMRegisters::S0, base, Op2Immediate | (-offset >> 12) | (10 << 8)); 282 dtrDown(transferType, srcDst, ARMRegisters::S0, (-offset & 0xfff)); 283 283 } else { 284 284 moveImm(offset, ARMRegisters::S0); 285 dtr _ur(transferType, srcDst, base, ARMRegisters::S0);285 dtrUpRegister(transferType, srcDst, base, ARMRegisters::S0); 286 286 } 287 287 } … … 294 294 295 295 if (!offset) { 296 dtr _ur(transferType, srcDst, base, op2);296 dtrUpRegister(transferType, srcDst, base, op2); 297 297 return; 298 298 } 299 299 300 add _r(ARMRegisters::S1, base, op2);300 add(ARMRegisters::S1, base, op2); 301 301 dataTransfer32(transferType, srcDst, ARMRegisters::S1, offset); 302 302 } … … 306 306 if (offset >= 0) { 307 307 if (offset <= 0xff) 308 dtrh_u(transferType, srcDst, base, getOp2Half(offset));308 halfDtrUp(transferType, srcDst, base, getOp2Half(offset)); 309 309 else if (offset <= 0xffff) { 310 add _r(ARMRegisters::S0, base, Op2Immediate | (offset >> 8) | (12 << 8));311 dtrh_u(transferType, srcDst, ARMRegisters::S0, getOp2Half(offset & 0xff));310 add(ARMRegisters::S0, base, Op2Immediate | (offset >> 8) | (12 << 8)); 311 halfDtrUp(transferType, srcDst, ARMRegisters::S0, getOp2Half(offset & 0xff)); 312 312 } else { 313 313 moveImm(offset, ARMRegisters::S0); 314 dtrh_ur(transferType, srcDst, base, ARMRegisters::S0);314 halfDtrUpRegister(transferType, srcDst, base, ARMRegisters::S0); 315 315 } 316 316 } else { 317 317 if (offset >= -0xff) 318 dtrh_d(transferType, srcDst, base, getOp2Half(-offset));318 halfDtrDown(transferType, srcDst, base, getOp2Half(-offset)); 319 319 else if (offset >= -0xffff) { 320 sub _r(ARMRegisters::S0, base, Op2Immediate | (-offset >> 8) | (12 << 8));321 dtrh_d(transferType, srcDst, ARMRegisters::S0, getOp2Half(-offset & 0xff));320 sub(ARMRegisters::S0, base, Op2Immediate | (-offset >> 8) | (12 << 8)); 321 halfDtrDown(transferType, srcDst, ARMRegisters::S0, getOp2Half(-offset & 0xff)); 322 322 } else { 323 323 moveImm(offset, ARMRegisters::S0); 324 dtrh_ur(transferType, srcDst, base, ARMRegisters::S0);324 halfDtrUpRegister(transferType, srcDst, base, ARMRegisters::S0); 325 325 } 326 326 } … … 330 330 { 331 331 if (!scale && !offset) { 332 dtrh_ur(transferType, srcDst, base, index);332 halfDtrUpRegister(transferType, srcDst, base, index); 333 333 return; 334 334 } 335 335 336 add _r(ARMRegisters::S1, base, lsl(index, scale));336 add(ARMRegisters::S1, base, lsl(index, scale)); 337 337 dataTransfer16(transferType, srcDst, ARMRegisters::S1, offset); 338 338 } … … 343 343 if (!(offset & 0x3)) { 344 344 if (offset <= 0x3ff && offset >= 0) { 345 fdtr_u(transferType, srcDst, base, offset >> 2);345 doubleDtrUp(transferType, srcDst, base, offset >> 2); 346 346 return; 347 347 } 348 348 if (offset <= 0x3ffff && offset >= 0) { 349 add _r(ARMRegisters::S0, base, Op2Immediate | (offset >> 10) | (11 << 8));350 fdtr_u(transferType, srcDst, ARMRegisters::S0, (offset >> 2) & 0xff);349 add(ARMRegisters::S0, base, Op2Immediate | (offset >> 10) | (11 << 8)); 350 doubleDtrUp(transferType, srcDst, ARMRegisters::S0, (offset >> 2) & 0xff); 351 351 return; 352 352 } … … 354 354 355 355 if (offset <= 0x3ff && offset >= 0) { 356 fdtr_d(transferType, srcDst, base, offset >> 2);356 doubleDtrDown(transferType, srcDst, base, offset >> 2); 357 357 return; 358 358 } 359 359 if (offset <= 0x3ffff && offset >= 0) { 360 sub _r(ARMRegisters::S0, base, Op2Immediate | (offset >> 10) | (11 << 8));361 fdtr_d(transferType, srcDst, ARMRegisters::S0, (offset >> 2) & 0xff);360 sub(ARMRegisters::S0, base, Op2Immediate | (offset >> 10) | (11 << 8)); 361 doubleDtrDown(transferType, srcDst, ARMRegisters::S0, (offset >> 2) & 0xff); 362 362 return; 363 363 } … … 366 366 367 367 moveImm(offset, ARMRegisters::S0); 368 add _r(ARMRegisters::S0, ARMRegisters::S0, base);369 fdtr_u(transferType, srcDst, ARMRegisters::S0, 0);368 add(ARMRegisters::S0, ARMRegisters::S0, base); 369 doubleDtrUp(transferType, srcDst, ARMRegisters::S0, 0); 370 370 } 371 371 372 372 void ARMAssembler::baseIndexTransferFloat(DataTransferTypeFloat transferType, FPRegisterID srcDst, RegisterID base, RegisterID index, int scale, int32_t offset) 373 373 { 374 add _r(ARMRegisters::S1, base, lsl(index, scale));374 add(ARMRegisters::S1, base, lsl(index, scale)); 375 375 dataTransferFloat(transferType, srcDst, ARMRegisters::S1, offset); 376 376 } -
trunk/Source/JavaScriptCore/assembler/ARMAssembler.h
r124930 r125541 269 269 } 270 270 271 void and_r(int rd, int rn, ARMWord op2, Condition cc = AL)271 void bitAnd(int rd, int rn, ARMWord op2, Condition cc = AL) 272 272 { 273 273 emitInstruction(toARMWord(cc) | AND, rd, rn, op2); 274 274 } 275 275 276 void ands_r(int rd, int rn, ARMWord op2, Condition cc = AL)276 void bitAnds(int rd, int rn, ARMWord op2, Condition cc = AL) 277 277 { 278 278 emitInstruction(toARMWord(cc) | AND | SetConditionalCodes, rd, rn, op2); 279 279 } 280 280 281 void eor _r(int rd, int rn, ARMWord op2, Condition cc = AL)281 void eor(int rd, int rn, ARMWord op2, Condition cc = AL) 282 282 { 283 283 emitInstruction(toARMWord(cc) | EOR, rd, rn, op2); 284 284 } 285 285 286 void eors _r(int rd, int rn, ARMWord op2, Condition cc = AL)286 void eors(int rd, int rn, ARMWord op2, Condition cc = AL) 287 287 { 288 288 emitInstruction(toARMWord(cc) | EOR | SetConditionalCodes, rd, rn, op2); 289 289 } 290 290 291 void sub _r(int rd, int rn, ARMWord op2, Condition cc = AL)291 void sub(int rd, int rn, ARMWord op2, Condition cc = AL) 292 292 { 293 293 emitInstruction(toARMWord(cc) | SUB, rd, rn, op2); 294 294 } 295 295 296 void subs _r(int rd, int rn, ARMWord op2, Condition cc = AL)296 void subs(int rd, int rn, ARMWord op2, Condition cc = AL) 297 297 { 298 298 emitInstruction(toARMWord(cc) | SUB | SetConditionalCodes, rd, rn, op2); 299 299 } 300 300 301 void rsb _r(int rd, int rn, ARMWord op2, Condition cc = AL)301 void rsb(int rd, int rn, ARMWord op2, Condition cc = AL) 302 302 { 303 303 emitInstruction(toARMWord(cc) | RSB, rd, rn, op2); 304 304 } 305 305 306 void rsbs _r(int rd, int rn, ARMWord op2, Condition cc = AL)306 void rsbs(int rd, int rn, ARMWord op2, Condition cc = AL) 307 307 { 308 308 emitInstruction(toARMWord(cc) | RSB | SetConditionalCodes, rd, rn, op2); 309 309 } 310 310 311 void add _r(int rd, int rn, ARMWord op2, Condition cc = AL)311 void add(int rd, int rn, ARMWord op2, Condition cc = AL) 312 312 { 313 313 emitInstruction(toARMWord(cc) | ADD, rd, rn, op2); 314 314 } 315 315 316 void adds _r(int rd, int rn, ARMWord op2, Condition cc = AL)316 void adds(int rd, int rn, ARMWord op2, Condition cc = AL) 317 317 { 318 318 emitInstruction(toARMWord(cc) | ADD | SetConditionalCodes, rd, rn, op2); 319 319 } 320 320 321 void adc _r(int rd, int rn, ARMWord op2, Condition cc = AL)321 void adc(int rd, int rn, ARMWord op2, Condition cc = AL) 322 322 { 323 323 emitInstruction(toARMWord(cc) | ADC, rd, rn, op2); 324 324 } 325 325 326 void adcs _r(int rd, int rn, ARMWord op2, Condition cc = AL)326 void adcs(int rd, int rn, ARMWord op2, Condition cc = AL) 327 327 { 328 328 emitInstruction(toARMWord(cc) | ADC | SetConditionalCodes, rd, rn, op2); 329 329 } 330 330 331 void sbc _r(int rd, int rn, ARMWord op2, Condition cc = AL)331 void sbc(int rd, int rn, ARMWord op2, Condition cc = AL) 332 332 { 333 333 emitInstruction(toARMWord(cc) | SBC, rd, rn, op2); 334 334 } 335 335 336 void sbcs _r(int rd, int rn, ARMWord op2, Condition cc = AL)336 void sbcs(int rd, int rn, ARMWord op2, Condition cc = AL) 337 337 { 338 338 emitInstruction(toARMWord(cc) | SBC | SetConditionalCodes, rd, rn, op2); 339 339 } 340 340 341 void rsc _r(int rd, int rn, ARMWord op2, Condition cc = AL)341 void rsc(int rd, int rn, ARMWord op2, Condition cc = AL) 342 342 { 343 343 emitInstruction(toARMWord(cc) | RSC, rd, rn, op2); 344 344 } 345 345 346 void rscs _r(int rd, int rn, ARMWord op2, Condition cc = AL)346 void rscs(int rd, int rn, ARMWord op2, Condition cc = AL) 347 347 { 348 348 emitInstruction(toARMWord(cc) | RSC | SetConditionalCodes, rd, rn, op2); 349 349 } 350 350 351 void tst _r(int rn, ARMWord op2, Condition cc = AL)351 void tst(int rn, ARMWord op2, Condition cc = AL) 352 352 { 353 353 emitInstruction(toARMWord(cc) | TST | SetConditionalCodes, 0, rn, op2); 354 354 } 355 355 356 void teq _r(int rn, ARMWord op2, Condition cc = AL)356 void teq(int rn, ARMWord op2, Condition cc = AL) 357 357 { 358 358 emitInstruction(toARMWord(cc) | TEQ | SetConditionalCodes, 0, rn, op2); 359 359 } 360 360 361 void cmp _r(int rn, ARMWord op2, Condition cc = AL)361 void cmp(int rn, ARMWord op2, Condition cc = AL) 362 362 { 363 363 emitInstruction(toARMWord(cc) | CMP | SetConditionalCodes, 0, rn, op2); 364 364 } 365 365 366 void cmn _r(int rn, ARMWord op2, Condition cc = AL)366 void cmn(int rn, ARMWord op2, Condition cc = AL) 367 367 { 368 368 emitInstruction(toARMWord(cc) | CMN | SetConditionalCodes, 0, rn, op2); 369 369 } 370 370 371 void orr _r(int rd, int rn, ARMWord op2, Condition cc = AL)371 void orr(int rd, int rn, ARMWord op2, Condition cc = AL) 372 372 { 373 373 emitInstruction(toARMWord(cc) | ORR, rd, rn, op2); 374 374 } 375 375 376 void orrs _r(int rd, int rn, ARMWord op2, Condition cc = AL)376 void orrs(int rd, int rn, ARMWord op2, Condition cc = AL) 377 377 { 378 378 emitInstruction(toARMWord(cc) | ORR | SetConditionalCodes, rd, rn, op2); 379 379 } 380 380 381 void mov _r(int rd, ARMWord op2, Condition cc = AL)381 void mov(int rd, ARMWord op2, Condition cc = AL) 382 382 { 383 383 emitInstruction(toARMWord(cc) | MOV, rd, ARMRegisters::r0, op2); … … 385 385 386 386 #if WTF_ARM_ARCH_AT_LEAST(7) 387 void movw _r(int rd, ARMWord op2, Condition cc = AL)387 void movw(int rd, ARMWord op2, Condition cc = AL) 388 388 { 389 389 ASSERT((op2 | 0xf0fff) == 0xf0fff); … … 391 391 } 392 392 393 void movt _r(int rd, ARMWord op2, Condition cc = AL)393 void movt(int rd, ARMWord op2, Condition cc = AL) 394 394 { 395 395 ASSERT((op2 | 0xf0fff) == 0xf0fff); … … 398 398 #endif 399 399 400 void movs _r(int rd, ARMWord op2, Condition cc = AL)400 void movs(int rd, ARMWord op2, Condition cc = AL) 401 401 { 402 402 emitInstruction(toARMWord(cc) | MOV | SetConditionalCodes, rd, ARMRegisters::r0, op2); 403 403 } 404 404 405 void bic _r(int rd, int rn, ARMWord op2, Condition cc = AL)405 void bic(int rd, int rn, ARMWord op2, Condition cc = AL) 406 406 { 407 407 emitInstruction(toARMWord(cc) | BIC, rd, rn, op2); 408 408 } 409 409 410 void bics _r(int rd, int rn, ARMWord op2, Condition cc = AL)410 void bics(int rd, int rn, ARMWord op2, Condition cc = AL) 411 411 { 412 412 emitInstruction(toARMWord(cc) | BIC | SetConditionalCodes, rd, rn, op2); 413 413 } 414 414 415 void mvn _r(int rd, ARMWord op2, Condition cc = AL)415 void mvn(int rd, ARMWord op2, Condition cc = AL) 416 416 { 417 417 emitInstruction(toARMWord(cc) | MVN, rd, ARMRegisters::r0, op2); 418 418 } 419 419 420 void mvns _r(int rd, ARMWord op2, Condition cc = AL)420 void mvns(int rd, ARMWord op2, Condition cc = AL) 421 421 { 422 422 emitInstruction(toARMWord(cc) | MVN | SetConditionalCodes, rd, ARMRegisters::r0, op2); 423 423 } 424 424 425 void mul _r(int rd, int rn, int rm, Condition cc = AL)425 void mul(int rd, int rn, int rm, Condition cc = AL) 426 426 { 427 427 m_buffer.putInt(toARMWord(cc) | MUL | RN(rd) | RS(rn) | RM(rm)); 428 428 } 429 429 430 void muls _r(int rd, int rn, int rm, Condition cc = AL)430 void muls(int rd, int rn, int rm, Condition cc = AL) 431 431 { 432 432 m_buffer.putInt(toARMWord(cc) | MUL | SetConditionalCodes | RN(rd) | RS(rn) | RM(rm)); 433 433 } 434 434 435 void mull _r(int rdhi, int rdlo, int rn, int rm, Condition cc = AL)435 void mull(int rdhi, int rdlo, int rn, int rm, Condition cc = AL) 436 436 { 437 437 m_buffer.putInt(toARMWord(cc) | MULL | RN(rdhi) | RD(rdlo) | RS(rn) | RM(rm)); 438 438 } 439 439 440 void vmov_f64 _r(int dd, int dm, Condition cc = AL)440 void vmov_f64(int dd, int dm, Condition cc = AL) 441 441 { 442 442 emitDoublePrecisionInstruction(toARMWord(cc) | VMOV_F64, dd, 0, dm); 443 443 } 444 444 445 void vadd_f64 _r(int dd, int dn, int dm, Condition cc = AL)445 void vadd_f64(int dd, int dn, int dm, Condition cc = AL) 446 446 { 447 447 emitDoublePrecisionInstruction(toARMWord(cc) | VADD_F64, dd, dn, dm); 448 448 } 449 449 450 void vdiv_f64 _r(int dd, int dn, int dm, Condition cc = AL)450 void vdiv_f64(int dd, int dn, int dm, Condition cc = AL) 451 451 { 452 452 emitDoublePrecisionInstruction(toARMWord(cc) | VDIV_F64, dd, dn, dm); 453 453 } 454 454 455 void vsub_f64 _r(int dd, int dn, int dm, Condition cc = AL)455 void vsub_f64(int dd, int dn, int dm, Condition cc = AL) 456 456 { 457 457 emitDoublePrecisionInstruction(toARMWord(cc) | VSUB_F64, dd, dn, dm); 458 458 } 459 459 460 void vmul_f64 _r(int dd, int dn, int dm, Condition cc = AL)460 void vmul_f64(int dd, int dn, int dm, Condition cc = AL) 461 461 { 462 462 emitDoublePrecisionInstruction(toARMWord(cc) | VMUL_F64, dd, dn, dm); 463 463 } 464 464 465 void vcmp_f64 _r(int dd, int dm, Condition cc = AL)465 void vcmp_f64(int dd, int dm, Condition cc = AL) 466 466 { 467 467 emitDoublePrecisionInstruction(toARMWord(cc) | VCMP_F64, dd, 0, dm); 468 468 } 469 469 470 void vsqrt_f64 _r(int dd, int dm, Condition cc = AL)470 void vsqrt_f64(int dd, int dm, Condition cc = AL) 471 471 { 472 472 emitDoublePrecisionInstruction(toARMWord(cc) | VSQRT_F64, dd, 0, dm); 473 473 } 474 474 475 void vabs_f64 _r(int dd, int dm, Condition cc = AL)475 void vabs_f64(int dd, int dm, Condition cc = AL) 476 476 { 477 477 emitDoublePrecisionInstruction(toARMWord(cc) | VABS_F64, dd, 0, dm); 478 478 } 479 479 480 void vneg_f64 _r(int dd, int dm, Condition cc = AL)480 void vneg_f64(int dd, int dm, Condition cc = AL) 481 481 { 482 482 emitDoublePrecisionInstruction(toARMWord(cc) | VNEG_F64, dd, 0, dm); 483 483 } 484 484 485 void ldr _imm(int rd, ARMWord imm, Condition cc = AL)485 void ldrImmediate(int rd, ARMWord imm, Condition cc = AL) 486 486 { 487 487 m_buffer.putIntWithConstantInt(toARMWord(cc) | LoadUint32 | DataTransferUp | RN(ARMRegisters::pc) | RD(rd), imm, true); 488 488 } 489 489 490 void ldr _un_imm(int rd, ARMWord imm, Condition cc = AL)490 void ldrUniqueImmediate(int rd, ARMWord imm, Condition cc = AL) 491 491 { 492 492 m_buffer.putIntWithConstantInt(toARMWord(cc) | LoadUint32 | DataTransferUp | RN(ARMRegisters::pc) | RD(rd), imm); 493 493 } 494 494 495 void dtr _u(DataTransferTypeA transferType, int rd, int rb, ARMWord op2, Condition cc = AL)495 void dtrUp(DataTransferTypeA transferType, int rd, int rb, ARMWord op2, Condition cc = AL) 496 496 { 497 497 emitInstruction(toARMWord(cc) | transferType | DataTransferUp, rd, rb, op2); 498 498 } 499 499 500 void dtr _ur(DataTransferTypeA transferType, int rd, int rb, int rm, Condition cc = AL)500 void dtrUpRegister(DataTransferTypeA transferType, int rd, int rb, int rm, Condition cc = AL) 501 501 { 502 502 emitInstruction(toARMWord(cc) | transferType | DataTransferUp | Op2IsRegisterArgument, rd, rb, rm); 503 503 } 504 504 505 void dtr _d(DataTransferTypeA transferType, int rd, int rb, ARMWord op2, Condition cc = AL)505 void dtrDown(DataTransferTypeA transferType, int rd, int rb, ARMWord op2, Condition cc = AL) 506 506 { 507 507 emitInstruction(toARMWord(cc) | transferType, rd, rb, op2); 508 508 } 509 509 510 void dtr _dr(DataTransferTypeA transferType, int rd, int rb, int rm, Condition cc = AL)510 void dtrDownRegister(DataTransferTypeA transferType, int rd, int rb, int rm, Condition cc = AL) 511 511 { 512 512 emitInstruction(toARMWord(cc) | transferType | Op2IsRegisterArgument, rd, rb, rm); 513 513 } 514 514 515 void dtrh_u(DataTransferTypeB transferType, int rd, int rb, ARMWord op2, Condition cc = AL)515 void halfDtrUp(DataTransferTypeB transferType, int rd, int rb, ARMWord op2, Condition cc = AL) 516 516 { 517 517 emitInstruction(toARMWord(cc) | transferType | DataTransferUp, rd, rb, op2); 518 518 } 519 519 520 void dtrh_ur(DataTransferTypeB transferType, int rd, int rn, int rm, Condition cc = AL)520 void halfDtrUpRegister(DataTransferTypeB transferType, int rd, int rn, int rm, Condition cc = AL) 521 521 { 522 522 emitInstruction(toARMWord(cc) | transferType | DataTransferUp, rd, rn, rm); 523 523 } 524 524 525 void dtrh_d(DataTransferTypeB transferType, int rd, int rb, ARMWord op2, Condition cc = AL)525 void halfDtrDown(DataTransferTypeB transferType, int rd, int rb, ARMWord op2, Condition cc = AL) 526 526 { 527 527 emitInstruction(toARMWord(cc) | transferType, rd, rb, op2); 528 528 } 529 529 530 void dtrh_dr(DataTransferTypeB transferType, int rd, int rn, int rm, Condition cc = AL)530 void halfDtrDownRegister(DataTransferTypeB transferType, int rd, int rn, int rm, Condition cc = AL) 531 531 { 532 532 emitInstruction(toARMWord(cc) | transferType, rd, rn, rm); 533 533 } 534 534 535 void fdtr_u(DataTransferTypeFloat type, int rd, int rb, ARMWord op2, Condition cc = AL)535 void doubleDtrUp(DataTransferTypeFloat type, int rd, int rb, ARMWord op2, Condition cc = AL) 536 536 { 537 537 ASSERT(op2 <= 0xff && rd <= 15); … … 540 540 } 541 541 542 void fdtr_d(DataTransferTypeFloat type, int rd, int rb, ARMWord op2, Condition cc = AL)542 void doubleDtrDown(DataTransferTypeFloat type, int rd, int rb, ARMWord op2, Condition cc = AL) 543 543 { 544 544 ASSERT(op2 <= 0xff && rd <= 15); … … 547 547 } 548 548 549 void push _r(int reg, Condition cc = AL)549 void push(int reg, Condition cc = AL) 550 550 { 551 551 ASSERT(ARMWord(reg) <= 0xf); … … 553 553 } 554 554 555 void pop _r(int reg, Condition cc = AL)555 void pop(int reg, Condition cc = AL) 556 556 { 557 557 ASSERT(ARMWord(reg) <= 0xf); … … 559 559 } 560 560 561 inline void poke _r(int reg, Condition cc = AL)562 { 563 dtr _d(StoreUint32, ARMRegisters::sp, 0, reg, cc);564 } 565 566 inline void peek _r(int reg, Condition cc = AL)567 { 568 dtr _u(LoadUint32, reg, ARMRegisters::sp, 0, cc);569 } 570 571 void vmov_vfp64 _r(int sm, int rt, int rt2, Condition cc = AL)561 inline void poke(int reg, Condition cc = AL) 562 { 563 dtrDown(StoreUint32, ARMRegisters::sp, 0, reg, cc); 564 } 565 566 inline void peek(int reg, Condition cc = AL) 567 { 568 dtrUp(LoadUint32, reg, ARMRegisters::sp, 0, cc); 569 } 570 571 void vmov_vfp64(int sm, int rt, int rt2, Condition cc = AL) 572 572 { 573 573 ASSERT(rt != rt2); … … 575 575 } 576 576 577 void vmov_arm64 _r(int rt, int rt2, int sm, Condition cc = AL)577 void vmov_arm64(int rt, int rt2, int sm, Condition cc = AL) 578 578 { 579 579 ASSERT(rt != rt2); … … 581 581 } 582 582 583 void vmov_vfp32 _r(int sn, int rt, Condition cc = AL)583 void vmov_vfp32(int sn, int rt, Condition cc = AL) 584 584 { 585 585 ASSERT(rt <= 15); … … 587 587 } 588 588 589 void vmov_arm32 _r(int rt, int sn, Condition cc = AL)589 void vmov_arm32(int rt, int sn, Condition cc = AL) 590 590 { 591 591 ASSERT(rt <= 15); … … 593 593 } 594 594 595 void vcvt_f64_s32 _r(int dd, int sm, Condition cc = AL)595 void vcvt_f64_s32(int dd, int sm, Condition cc = AL) 596 596 { 597 597 ASSERT(!(sm & 0x1)); // sm must be divisible by 2 … … 599 599 } 600 600 601 void vcvt_s32_f64 _r(int sd, int dm, Condition cc = AL)601 void vcvt_s32_f64(int sd, int dm, Condition cc = AL) 602 602 { 603 603 ASSERT(!(sd & 0x1)); // sd must be divisible by 2 … … 605 605 } 606 606 607 void vcvt_u32_f64 _r(int sd, int dm, Condition cc = AL)607 void vcvt_u32_f64(int sd, int dm, Condition cc = AL) 608 608 { 609 609 ASSERT(!(sd & 0x1)); // sd must be divisible by 2 … … 611 611 } 612 612 613 void vcvt_f64_f32 _r(int dd, int sm, Condition cc = AL)613 void vcvt_f64_f32(int dd, int sm, Condition cc = AL) 614 614 { 615 615 ASSERT(dd <= 15 && sm <= 15); … … 617 617 } 618 618 619 void vcvt_f32_f64 _r(int dd, int sm, Condition cc = AL)619 void vcvt_f32_f64(int dd, int sm, Condition cc = AL) 620 620 { 621 621 ASSERT(dd <= 15 && sm <= 15); … … 628 628 } 629 629 630 void clz _r(int rd, int rm, Condition cc = AL)630 void clz(int rd, int rm, Condition cc = AL) 631 631 { 632 632 m_buffer.putInt(toARMWord(cc) | CLZ | RD(rd) | RM(rm)); … … 675 675 } 676 676 677 static ARMWord lsl _r(int reg, int shiftReg)677 static ARMWord lslRegister(int reg, int shiftReg) 678 678 { 679 679 ASSERT(reg <= ARMRegisters::pc); … … 682 682 } 683 683 684 static ARMWord lsr _r(int reg, int shiftReg)684 static ARMWord lsrRegister(int reg, int shiftReg) 685 685 { 686 686 ASSERT(reg <= ARMRegisters::pc); … … 689 689 } 690 690 691 static ARMWord asr _r(int reg, int shiftReg)691 static ARMWord asrRegister(int reg, int shiftReg) 692 692 { 693 693 ASSERT(reg <= ARMRegisters::pc); … … 743 743 { 744 744 while (!m_buffer.isAligned(alignment)) 745 mov _r(ARMRegisters::r0, ARMRegisters::r0);745 mov(ARMRegisters::r0, ARMRegisters::r0); 746 746 747 747 return label(); … … 752 752 ensureSpace(sizeof(ARMWord), sizeof(ARMWord)); 753 753 m_jumps.append(m_buffer.codeSize() | (useConstantPool & 0x1)); 754 ldr _un_imm(rd, InvalidBranchTarget, cc);754 ldrUniqueImmediate(rd, InvalidBranchTarget, cc); 755 755 return m_buffer.label(); 756 756 } … … 768 768 void vmov(RegisterID rd1, RegisterID rd2, FPRegisterID rn) 769 769 { 770 vmov_arm64 _r(rd1, rd2, rn);770 vmov_arm64(rd1, rd2, rn); 771 771 } 772 772 773 773 void vmov(FPRegisterID rd, RegisterID rn1, RegisterID rn2) 774 774 { 775 vmov_vfp64 _r(rd, rn1, rn2);775 vmov_vfp64(rd, rn1, rn2); 776 776 } 777 777 -
trunk/Source/JavaScriptCore/assembler/MacroAssemblerARM.cpp
r124930 r125541 77 77 78 78 if (address.offset >= 0 && address.offset + 0x2 <= 0xff) { 79 m_assembler.add _r(ARMRegisters::S0, address.base, op2);80 m_assembler. dtrh_u(ARMAssembler::LoadUint16, dest, ARMRegisters::S0, ARMAssembler::getOp2Half(address.offset));81 m_assembler. dtrh_u(ARMAssembler::LoadUint16, ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::getOp2Half(address.offset + 0x2));79 m_assembler.add(ARMRegisters::S0, address.base, op2); 80 m_assembler.halfDtrUp(ARMAssembler::LoadUint16, dest, ARMRegisters::S0, ARMAssembler::getOp2Half(address.offset)); 81 m_assembler.halfDtrUp(ARMAssembler::LoadUint16, ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::getOp2Half(address.offset + 0x2)); 82 82 } else if (address.offset < 0 && address.offset >= -0xff) { 83 m_assembler.add _r(ARMRegisters::S0, address.base, op2);84 m_assembler. dtrh_d(ARMAssembler::LoadUint16, dest, ARMRegisters::S0, ARMAssembler::getOp2Half(-address.offset));85 m_assembler. dtrh_d(ARMAssembler::LoadUint16, ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::getOp2Half(-address.offset - 0x2));83 m_assembler.add(ARMRegisters::S0, address.base, op2); 84 m_assembler.halfDtrDown(ARMAssembler::LoadUint16, dest, ARMRegisters::S0, ARMAssembler::getOp2Half(-address.offset)); 85 m_assembler.halfDtrDown(ARMAssembler::LoadUint16, ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::getOp2Half(-address.offset - 0x2)); 86 86 } else { 87 87 m_assembler.moveImm(address.offset, ARMRegisters::S0); 88 m_assembler.add _r(ARMRegisters::S0, ARMRegisters::S0, op2);89 m_assembler. dtrh_ur(ARMAssembler::LoadUint16, dest, address.base, ARMRegisters::S0);90 m_assembler.add _r(ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::Op2Immediate | 0x2);91 m_assembler. dtrh_ur(ARMAssembler::LoadUint16, ARMRegisters::S0, address.base, ARMRegisters::S0);88 m_assembler.add(ARMRegisters::S0, ARMRegisters::S0, op2); 89 m_assembler.halfDtrUpRegister(ARMAssembler::LoadUint16, dest, address.base, ARMRegisters::S0); 90 m_assembler.add(ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::Op2Immediate | 0x2); 91 m_assembler.halfDtrUpRegister(ARMAssembler::LoadUint16, ARMRegisters::S0, address.base, ARMRegisters::S0); 92 92 } 93 m_assembler.orr _r(dest, dest, m_assembler.lsl(ARMRegisters::S0, 16));93 m_assembler.orr(dest, dest, m_assembler.lsl(ARMRegisters::S0, 16)); 94 94 } 95 95 #endif -
trunk/Source/JavaScriptCore/assembler/MacroAssemblerARM.h
r124930 r125541 87 87 void add32(RegisterID src, RegisterID dest) 88 88 { 89 m_assembler.adds _r(dest, dest, src);89 m_assembler.adds(dest, dest, src); 90 90 } 91 91 92 92 void add32(RegisterID op1, RegisterID op2, RegisterID dest) 93 93 { 94 m_assembler.adds _r(dest, op1, op2);94 m_assembler.adds(dest, op1, op2); 95 95 } 96 96 … … 104 104 void add32(TrustedImm32 imm, RegisterID dest) 105 105 { 106 m_assembler.adds _r(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0));106 m_assembler.adds(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0)); 107 107 } 108 108 … … 110 110 { 111 111 move(TrustedImmPtr(src.m_ptr), ARMRegisters::S1); 112 m_assembler.dtr _u(ARMAssembler::LoadUint32, ARMRegisters::S1, ARMRegisters::S1, 0);112 m_assembler.dtrUp(ARMAssembler::LoadUint32, ARMRegisters::S1, ARMRegisters::S1, 0); 113 113 add32(ARMRegisters::S1, dest); 114 114 } … … 122 122 void add32(RegisterID src, TrustedImm32 imm, RegisterID dest) 123 123 { 124 m_assembler.adds _r(dest, src, m_assembler.getImm(imm.m_value, ARMRegisters::S0));124 m_assembler.adds(dest, src, m_assembler.getImm(imm.m_value, ARMRegisters::S0)); 125 125 } 126 126 127 127 void and32(RegisterID src, RegisterID dest) 128 128 { 129 m_assembler. ands_r(dest, dest, src);129 m_assembler.bitAnds(dest, dest, src); 130 130 } 131 131 132 132 void and32(RegisterID op1, RegisterID op2, RegisterID dest) 133 133 { 134 m_assembler. ands_r(dest, op1, op2);134 m_assembler.bitAnds(dest, op1, op2); 135 135 } 136 136 … … 139 139 ARMWord w = m_assembler.getImm(imm.m_value, ARMRegisters::S0, true); 140 140 if (w & ARMAssembler::Op2InvertedImmediate) 141 m_assembler.bics _r(dest, dest, w & ~ARMAssembler::Op2InvertedImmediate);141 m_assembler.bics(dest, dest, w & ~ARMAssembler::Op2InvertedImmediate); 142 142 else 143 m_assembler. ands_r(dest, dest, w);143 m_assembler.bitAnds(dest, dest, w); 144 144 } 145 145 … … 148 148 ARMWord w = m_assembler.getImm(imm.m_value, ARMRegisters::S0, true); 149 149 if (w & ARMAssembler::Op2InvertedImmediate) 150 m_assembler.bics _r(dest, src, w & ~ARMAssembler::Op2InvertedImmediate);150 m_assembler.bics(dest, src, w & ~ARMAssembler::Op2InvertedImmediate); 151 151 else 152 m_assembler. ands_r(dest, src, w);152 m_assembler.bitAnds(dest, src, w); 153 153 } 154 154 … … 161 161 { 162 162 ARMWord w = ARMAssembler::getOp2Byte(0x1f); 163 m_assembler. and_r(ARMRegisters::S0, shiftAmount, w);164 165 m_assembler.movs _r(dest, m_assembler.lsl_r(src, ARMRegisters::S0));163 m_assembler.bitAnd(ARMRegisters::S0, shiftAmount, w); 164 165 m_assembler.movs(dest, m_assembler.lslRegister(src, ARMRegisters::S0)); 166 166 } 167 167 168 168 void lshift32(TrustedImm32 imm, RegisterID dest) 169 169 { 170 m_assembler.movs _r(dest, m_assembler.lsl(dest, imm.m_value & 0x1f));170 m_assembler.movs(dest, m_assembler.lsl(dest, imm.m_value & 0x1f)); 171 171 } 172 172 173 173 void lshift32(RegisterID src, TrustedImm32 imm, RegisterID dest) 174 174 { 175 m_assembler.movs _r(dest, m_assembler.lsl(src, imm.m_value & 0x1f));175 m_assembler.movs(dest, m_assembler.lsl(src, imm.m_value & 0x1f)); 176 176 } 177 177 … … 189 189 } 190 190 } 191 m_assembler.muls _r(dest, op1, op2);191 m_assembler.muls(dest, op1, op2); 192 192 } 193 193 … … 200 200 { 201 201 move(imm, ARMRegisters::S0); 202 m_assembler.muls _r(dest, src, ARMRegisters::S0);202 m_assembler.muls(dest, src, ARMRegisters::S0); 203 203 } 204 204 … … 210 210 void or32(RegisterID src, RegisterID dest) 211 211 { 212 m_assembler.orrs _r(dest, dest, src);212 m_assembler.orrs(dest, dest, src); 213 213 } 214 214 215 215 void or32(TrustedImm32 imm, RegisterID dest) 216 216 { 217 m_assembler.orrs _r(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0));217 m_assembler.orrs(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0)); 218 218 } 219 219 220 220 void or32(TrustedImm32 imm, RegisterID src, RegisterID dest) 221 221 { 222 m_assembler.orrs _r(dest, src, m_assembler.getImm(imm.m_value, ARMRegisters::S0));222 m_assembler.orrs(dest, src, m_assembler.getImm(imm.m_value, ARMRegisters::S0)); 223 223 } 224 224 225 225 void or32(RegisterID op1, RegisterID op2, RegisterID dest) 226 226 { 227 m_assembler.orrs _r(dest, op1, op2);227 m_assembler.orrs(dest, op1, op2); 228 228 } 229 229 … … 236 236 { 237 237 ARMWord w = ARMAssembler::getOp2Byte(0x1f); 238 m_assembler. and_r(ARMRegisters::S0, shiftAmount, w);239 240 m_assembler.movs _r(dest, m_assembler.asr_r(src, ARMRegisters::S0));238 m_assembler.bitAnd(ARMRegisters::S0, shiftAmount, w); 239 240 m_assembler.movs(dest, m_assembler.asrRegister(src, ARMRegisters::S0)); 241 241 } 242 242 … … 248 248 void rshift32(RegisterID src, TrustedImm32 imm, RegisterID dest) 249 249 { 250 m_assembler.movs _r(dest, m_assembler.asr(src, imm.m_value & 0x1f));250 m_assembler.movs(dest, m_assembler.asr(src, imm.m_value & 0x1f)); 251 251 } 252 252 … … 259 259 { 260 260 ARMWord w = ARMAssembler::getOp2Byte(0x1f); 261 m_assembler. and_r(ARMRegisters::S0, shiftAmount, w);262 263 m_assembler.movs _r(dest, m_assembler.lsr_r(src, ARMRegisters::S0));261 m_assembler.bitAnd(ARMRegisters::S0, shiftAmount, w); 262 263 m_assembler.movs(dest, m_assembler.lsrRegister(src, ARMRegisters::S0)); 264 264 } 265 265 266 266 void urshift32(TrustedImm32 imm, RegisterID dest) 267 267 { 268 m_assembler.movs _r(dest, m_assembler.lsr(dest, imm.m_value & 0x1f));268 m_assembler.movs(dest, m_assembler.lsr(dest, imm.m_value & 0x1f)); 269 269 } 270 270 271 271 void urshift32(RegisterID src, TrustedImm32 imm, RegisterID dest) 272 272 { 273 m_assembler.movs _r(dest, m_assembler.lsr(src, imm.m_value & 0x1f));273 m_assembler.movs(dest, m_assembler.lsr(src, imm.m_value & 0x1f)); 274 274 } 275 275 276 276 void sub32(RegisterID src, RegisterID dest) 277 277 { 278 m_assembler.subs _r(dest, dest, src);278 m_assembler.subs(dest, dest, src); 279 279 } 280 280 281 281 void sub32(TrustedImm32 imm, RegisterID dest) 282 282 { 283 m_assembler.subs _r(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0));283 m_assembler.subs(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0)); 284 284 } 285 285 … … 299 299 void sub32(RegisterID src, TrustedImm32 imm, RegisterID dest) 300 300 { 301 m_assembler.subs _r(dest, src, m_assembler.getImm(imm.m_value, ARMRegisters::S0));301 m_assembler.subs(dest, src, m_assembler.getImm(imm.m_value, ARMRegisters::S0)); 302 302 } 303 303 … … 315 315 { 316 316 if (imm.m_value == -1) 317 m_assembler.mvns _r(dest, dest);317 m_assembler.mvns(dest, dest); 318 318 else 319 319 m_assembler.eors_r(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0)); … … 323 323 { 324 324 if (imm.m_value == -1) 325 m_assembler.mvns _r(dest, src);325 m_assembler.mvns(dest, src); 326 326 else 327 327 m_assembler.eors_r(dest, src, m_assembler.getImm(imm.m_value, ARMRegisters::S0)); … … 331 331 { 332 332 #if WTF_ARM_ARCH_AT_LEAST(5) 333 m_assembler.clz _r(dest, src);333 m_assembler.clz(dest, src); 334 334 #else 335 335 UNUSED_PARAM(src); … … 397 397 ConvertibleLoadLabel result(this); 398 398 ASSERT(address.offset >= 0 && address.offset <= 255); 399 m_assembler.dtr _u(ARMAssembler::LoadUint32, dest, address.base, address.offset);399 m_assembler.dtrUp(ARMAssembler::LoadUint32, dest, address.base, address.offset); 400 400 return result; 401 401 } … … 404 404 { 405 405 DataLabel32 dataLabel(this); 406 m_assembler.ldr _un_imm(ARMRegisters::S0, 0);407 m_assembler.dtr _ur(ARMAssembler::LoadUint32, dest, address.base, ARMRegisters::S0);406 m_assembler.ldrUniqueImmediate(ARMRegisters::S0, 0); 407 m_assembler.dtrUpRegister(ARMAssembler::LoadUint32, dest, address.base, ARMRegisters::S0); 408 408 return dataLabel; 409 409 } … … 419 419 ASSERT(isCompactPtrAlignedAddressOffset(address.offset)); 420 420 if (address.offset >= 0) 421 m_assembler.dtr _u(ARMAssembler::LoadUint32, dest, address.base, address.offset);421 m_assembler.dtrUp(ARMAssembler::LoadUint32, dest, address.base, address.offset); 422 422 else 423 m_assembler.dtr _d(ARMAssembler::LoadUint32, dest, address.base, address.offset);423 m_assembler.dtrDown(ARMAssembler::LoadUint32, dest, address.base, address.offset); 424 424 return dataLabel; 425 425 } … … 428 428 { 429 429 DataLabel32 dataLabel(this); 430 m_assembler.ldr _un_imm(ARMRegisters::S0, 0);431 m_assembler.dtr _ur(ARMAssembler::StoreUint32, src, address.base, ARMRegisters::S0);430 m_assembler.ldrUniqueImmediate(ARMRegisters::S0, 0); 431 m_assembler.dtrUpRegister(ARMAssembler::StoreUint32, src, address.base, ARMRegisters::S0); 432 432 return dataLabel; 433 433 } … … 467 467 void store32(RegisterID src, void* address) 468 468 { 469 m_assembler.ldr _un_imm(ARMRegisters::S0, reinterpret_cast<ARMWord>(address));470 m_assembler.dtr _u(ARMAssembler::StoreUint32, src, ARMRegisters::S0, 0);469 m_assembler.ldrUniqueImmediate(ARMRegisters::S0, reinterpret_cast<ARMWord>(address)); 470 m_assembler.dtrUp(ARMAssembler::StoreUint32, src, ARMRegisters::S0, 0); 471 471 } 472 472 473 473 void store32(TrustedImm32 imm, void* address) 474 474 { 475 m_assembler.ldr _un_imm(ARMRegisters::S0, reinterpret_cast<ARMWord>(address));475 m_assembler.ldrUniqueImmediate(ARMRegisters::S0, reinterpret_cast<ARMWord>(address)); 476 476 m_assembler.moveImm(imm.m_value, ARMRegisters::S1); 477 m_assembler.dtr _u(ARMAssembler::StoreUint32, ARMRegisters::S1, ARMRegisters::S0, 0);477 m_assembler.dtrUp(ARMAssembler::StoreUint32, ARMRegisters::S1, ARMRegisters::S0, 0); 478 478 } 479 479 480 480 void pop(RegisterID dest) 481 481 { 482 m_assembler.pop _r(dest);482 m_assembler.pop(dest); 483 483 } 484 484 485 485 void push(RegisterID src) 486 486 { 487 m_assembler.push _r(src);487 m_assembler.push(src); 488 488 } 489 489 … … 508 508 { 509 509 if (src != dest) 510 m_assembler.mov _r(dest, src);510 m_assembler.mov(dest, src); 511 511 } 512 512 … … 518 518 void swap(RegisterID reg1, RegisterID reg2) 519 519 { 520 m_assembler.mov _r(ARMRegisters::S0, reg1);521 m_assembler.mov _r(reg1, reg2);522 m_assembler.mov _r(reg2, ARMRegisters::S0);520 m_assembler.mov(ARMRegisters::S0, reg1); 521 m_assembler.mov(reg1, reg2); 522 m_assembler.mov(reg2, ARMRegisters::S0); 523 523 } 524 524 … … 550 550 Jump branch32(RelationalCondition cond, RegisterID left, RegisterID right, int useConstantPool = 0) 551 551 { 552 m_assembler.cmp _r(left, right);552 m_assembler.cmp(left, right); 553 553 return Jump(m_assembler.jmp(ARMCondition(cond), useConstantPool)); 554 554 } … … 558 558 ARMWord tmp = (right.m_value == 0x80000000) ? ARMAssembler::InvalidImmediate : m_assembler.getOp2(-right.m_value); 559 559 if (tmp != ARMAssembler::InvalidImmediate) 560 m_assembler.cmn _r(left, tmp);560 m_assembler.cmn(left, tmp); 561 561 else 562 m_assembler.cmp _r(left, m_assembler.getImm(right.m_value, ARMRegisters::S0));562 m_assembler.cmp(left, m_assembler.getImm(right.m_value, ARMRegisters::S0)); 563 563 return Jump(m_assembler.jmp(ARMCondition(cond), useConstantPool)); 564 564 } … … 610 610 { 611 611 ASSERT((cond == Zero) || (cond == NonZero)); 612 m_assembler.tst _r(reg, mask);612 m_assembler.tst(reg, mask); 613 613 return Jump(m_assembler.jmp(ARMCondition(cond))); 614 614 } … … 619 619 ARMWord w = m_assembler.getImm(mask.m_value, ARMRegisters::S0, true); 620 620 if (w & ARMAssembler::Op2InvertedImmediate) 621 m_assembler.bics _r(ARMRegisters::S0, reg, w & ~ARMAssembler::Op2InvertedImmediate);621 m_assembler.bics(ARMRegisters::S0, reg, w & ~ARMAssembler::Op2InvertedImmediate); 622 622 else 623 m_assembler.tst _r(reg, w);623 m_assembler.tst(reg, w); 624 624 return Jump(m_assembler.jmp(ARMCondition(cond))); 625 625 } … … 706 706 } 707 707 } 708 m_assembler.mull _r(ARMRegisters::S1, dest, op1, op2);709 m_assembler.cmp _r(ARMRegisters::S1, m_assembler.asr(dest, 31));708 m_assembler.mull(ARMRegisters::S1, dest, op1, op2); 709 m_assembler.cmp(ARMRegisters::S1, m_assembler.asr(dest, 31)); 710 710 } 711 711 … … 764 764 { 765 765 ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero)); 766 m_assembler.subs _r(dest, op1, op2);766 m_assembler.subs(dest, op1, op2); 767 767 return Jump(m_assembler.jmp(ARMCondition(cond))); 768 768 } … … 810 810 void compare32(RelationalCondition cond, RegisterID left, RegisterID right, RegisterID dest) 811 811 { 812 m_assembler.cmp _r(left, right);813 m_assembler.mov _r(dest, ARMAssembler::getOp2Byte(0));814 m_assembler.mov _r(dest, ARMAssembler::getOp2Byte(1), ARMCondition(cond));812 m_assembler.cmp(left, right); 813 m_assembler.mov(dest, ARMAssembler::getOp2Byte(0)); 814 m_assembler.mov(dest, ARMAssembler::getOp2Byte(1), ARMCondition(cond)); 815 815 } 816 816 817 817 void compare32(RelationalCondition cond, RegisterID left, TrustedImm32 right, RegisterID dest) 818 818 { 819 m_assembler.cmp _r(left, m_assembler.getImm(right.m_value, ARMRegisters::S0));820 m_assembler.mov _r(dest, ARMAssembler::getOp2Byte(0));821 m_assembler.mov _r(dest, ARMAssembler::getOp2Byte(1), ARMCondition(cond));819 m_assembler.cmp(left, m_assembler.getImm(right.m_value, ARMRegisters::S0)); 820 m_assembler.mov(dest, ARMAssembler::getOp2Byte(0)); 821 m_assembler.mov(dest, ARMAssembler::getOp2Byte(1), ARMCondition(cond)); 822 822 } 823 823 … … 831 831 { 832 832 if (mask.m_value == -1) 833 m_assembler.cmp _r(0, reg);833 m_assembler.cmp(0, reg); 834 834 else 835 m_assembler.tst _r(reg, m_assembler.getImm(mask.m_value, ARMRegisters::S0));836 m_assembler.mov _r(dest, ARMAssembler::getOp2Byte(0));837 m_assembler.mov _r(dest, ARMAssembler::getOp2Byte(1), ARMCondition(cond));835 m_assembler.tst(reg, m_assembler.getImm(mask.m_value, ARMRegisters::S0)); 836 m_assembler.mov(dest, ARMAssembler::getOp2Byte(0)); 837 m_assembler.mov(dest, ARMAssembler::getOp2Byte(1), ARMCondition(cond)); 838 838 } 839 839 … … 852 852 void add32(TrustedImm32 imm, RegisterID src, RegisterID dest) 853 853 { 854 m_assembler.add _r(dest, src, m_assembler.getImm(imm.m_value, ARMRegisters::S0));854 m_assembler.add(dest, src, m_assembler.getImm(imm.m_value, ARMRegisters::S0)); 855 855 } 856 856 857 857 void add32(TrustedImm32 imm, AbsoluteAddress address) 858 858 { 859 m_assembler.ldr _un_imm(ARMRegisters::S1, reinterpret_cast<ARMWord>(address.m_ptr));860 m_assembler.dtr _u(ARMAssembler::LoadUint32, ARMRegisters::S1, ARMRegisters::S1, 0);859 m_assembler.ldrUniqueImmediate(ARMRegisters::S1, reinterpret_cast<ARMWord>(address.m_ptr)); 860 m_assembler.dtrUp(ARMAssembler::LoadUint32, ARMRegisters::S1, ARMRegisters::S1, 0); 861 861 add32(imm, ARMRegisters::S1); 862 m_assembler.ldr _un_imm(ARMRegisters::S0, reinterpret_cast<ARMWord>(address.m_ptr));863 m_assembler.dtr _u(ARMAssembler::StoreUint32, ARMRegisters::S1, ARMRegisters::S0, 0);862 m_assembler.ldrUniqueImmediate(ARMRegisters::S0, reinterpret_cast<ARMWord>(address.m_ptr)); 863 m_assembler.dtrUp(ARMAssembler::StoreUint32, ARMRegisters::S1, ARMRegisters::S0, 0); 864 864 } 865 865 866 866 void sub32(TrustedImm32 imm, AbsoluteAddress address) 867 867 { 868 m_assembler.ldr _un_imm(ARMRegisters::S1, reinterpret_cast<ARMWord>(address.m_ptr));869 m_assembler.dtr _u(ARMAssembler::LoadUint32, ARMRegisters::S1, ARMRegisters::S1, 0);868 m_assembler.ldrUniqueImmediate(ARMRegisters::S1, reinterpret_cast<ARMWord>(address.m_ptr)); 869 m_assembler.dtrUp(ARMAssembler::LoadUint32, ARMRegisters::S1, ARMRegisters::S1, 0); 870 870 sub32(imm, ARMRegisters::S1); 871 m_assembler.ldr _un_imm(ARMRegisters::S0, reinterpret_cast<ARMWord>(address.m_ptr));872 m_assembler.dtr _u(ARMAssembler::StoreUint32, ARMRegisters::S1, ARMRegisters::S0, 0);871 m_assembler.ldrUniqueImmediate(ARMRegisters::S0, reinterpret_cast<ARMWord>(address.m_ptr)); 872 m_assembler.dtrUp(ARMAssembler::StoreUint32, ARMRegisters::S1, ARMRegisters::S0, 0); 873 873 } 874 874 875 875 void load32(const void* address, RegisterID dest) 876 876 { 877 m_assembler.ldr _un_imm(ARMRegisters::S0, reinterpret_cast<ARMWord>(address));878 m_assembler.dtr _u(ARMAssembler::LoadUint32, dest, ARMRegisters::S0, 0);877 m_assembler.ldrUniqueImmediate(ARMRegisters::S0, reinterpret_cast<ARMWord>(address)); 878 m_assembler.dtrUp(ARMAssembler::LoadUint32, dest, ARMRegisters::S0, 0); 879 879 } 880 880 … … 894 894 { 895 895 ASSERT(scale >= 0 && scale <= 31); 896 m_assembler.add _r(ARMRegisters::pc, ARMRegisters::pc, m_assembler.lsl(index, scale));896 m_assembler.add(ARMRegisters::pc, ARMRegisters::pc, m_assembler.lsl(index, scale)); 897 897 898 898 // NOP the default prefetching 899 m_assembler.mov _r(ARMRegisters::r0, ARMRegisters::r0);899 m_assembler.mov(ARMRegisters::r0, ARMRegisters::r0); 900 900 } 901 901 … … 920 920 { 921 921 DataLabelPtr dataLabel(this); 922 m_assembler.ldr _un_imm(dest, reinterpret_cast<ARMWord>(initialValue.m_value));922 m_assembler.ldrUniqueImmediate(dest, reinterpret_cast<ARMWord>(initialValue.m_value)); 923 923 return dataLabel; 924 924 } … … 986 986 { 987 987 move(TrustedImm32(reinterpret_cast<ARMWord>(address)), ARMRegisters::S0); 988 m_assembler. fdtr_u(ARMAssembler::LoadDouble, dest, ARMRegisters::S0, 0);988 m_assembler.doubleDtrUp(ARMAssembler::LoadDouble, dest, ARMRegisters::S0, 0); 989 989 } 990 990 … … 1013 1013 { 1014 1014 if (src != dest) 1015 m_assembler.vmov_f64 _r(dest, src);1015 m_assembler.vmov_f64(dest, src); 1016 1016 } 1017 1017 1018 1018 void addDouble(FPRegisterID src, FPRegisterID dest) 1019 1019 { 1020 m_assembler.vadd_f64 _r(dest, dest, src);1020 m_assembler.vadd_f64(dest, dest, src); 1021 1021 } 1022 1022 1023 1023 void addDouble(FPRegisterID op1, FPRegisterID op2, FPRegisterID dest) 1024 1024 { 1025 m_assembler.vadd_f64 _r(dest, op1, op2);1025 m_assembler.vadd_f64(dest, op1, op2); 1026 1026 } 1027 1027 … … 1040 1040 void divDouble(FPRegisterID src, FPRegisterID dest) 1041 1041 { 1042 m_assembler.vdiv_f64 _r(dest, dest, src);1042 m_assembler.vdiv_f64(dest, dest, src); 1043 1043 } 1044 1044 1045 1045 void divDouble(FPRegisterID op1, FPRegisterID op2, FPRegisterID dest) 1046 1046 { 1047 m_assembler.vdiv_f64 _r(dest, op1, op2);1047 m_assembler.vdiv_f64(dest, op1, op2); 1048 1048 } 1049 1049 … … 1057 1057 void subDouble(FPRegisterID src, FPRegisterID dest) 1058 1058 { 1059 m_assembler.vsub_f64 _r(dest, dest, src);1059 m_assembler.vsub_f64(dest, dest, src); 1060 1060 } 1061 1061 1062 1062 void subDouble(FPRegisterID op1, FPRegisterID op2, FPRegisterID dest) 1063 1063 { 1064 m_assembler.vsub_f64 _r(dest, op1, op2);1064 m_assembler.vsub_f64(dest, op1, op2); 1065 1065 } 1066 1066 … … 1073 1073 void mulDouble(FPRegisterID src, FPRegisterID dest) 1074 1074 { 1075 m_assembler.vmul_f64 _r(dest, dest, src);1075 m_assembler.vmul_f64(dest, dest, src); 1076 1076 } 1077 1077 … … 1084 1084 void mulDouble(FPRegisterID op1, FPRegisterID op2, FPRegisterID dest) 1085 1085 { 1086 m_assembler.vmul_f64 _r(dest, op1, op2);1086 m_assembler.vmul_f64(dest, op1, op2); 1087 1087 } 1088 1088 1089 1089 void sqrtDouble(FPRegisterID src, FPRegisterID dest) 1090 1090 { 1091 m_assembler.vsqrt_f64 _r(dest, src);1091 m_assembler.vsqrt_f64(dest, src); 1092 1092 } 1093 1093 1094 1094 void absDouble(FPRegisterID src, FPRegisterID dest) 1095 1095 { 1096 m_assembler.vabs_f64 _r(dest, src);1096 m_assembler.vabs_f64(dest, src); 1097 1097 } 1098 1098 1099 1099 void negateDouble(FPRegisterID src, FPRegisterID dest) 1100 1100 { 1101 m_assembler.vneg_f64 _r(dest, src);1101 m_assembler.vneg_f64(dest, src); 1102 1102 } 1103 1103 1104 1104 void convertInt32ToDouble(RegisterID src, FPRegisterID dest) 1105 1105 { 1106 m_assembler.vmov_vfp32 _r(dest << 1, src);1107 m_assembler.vcvt_f64_s32 _r(dest, dest << 1);1106 m_assembler.vmov_vfp32(dest << 1, src); 1107 m_assembler.vcvt_f64_s32(dest, dest << 1); 1108 1108 } 1109 1109 … … 1123 1123 void convertFloatToDouble(FPRegisterID src, FPRegisterID dst) 1124 1124 { 1125 m_assembler.vcvt_f64_f32 _r(dst, src);1125 m_assembler.vcvt_f64_f32(dst, src); 1126 1126 } 1127 1127 1128 1128 void convertDoubleToFloat(FPRegisterID src, FPRegisterID dst) 1129 1129 { 1130 m_assembler.vcvt_f32_f64 _r(dst, src);1130 m_assembler.vcvt_f32_f64(dst, src); 1131 1131 } 1132 1132 1133 1133 Jump branchDouble(DoubleCondition cond, FPRegisterID left, FPRegisterID right) 1134 1134 { 1135 m_assembler.vcmp_f64 _r(left, right);1135 m_assembler.vcmp_f64(left, right); 1136 1136 m_assembler.vmrs_apsr(); 1137 1137 if (cond & DoubleConditionBitSpecial) 1138 m_assembler.cmp _r(ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::VS);1138 m_assembler.cmp(ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::VS); 1139 1139 return Jump(m_assembler.jmp(static_cast<ARMAssembler::Condition>(cond & ~DoubleConditionMask))); 1140 1140 } … … 1149 1149 truncateDoubleToInt32(src, dest); 1150 1150 1151 m_assembler.add _r(ARMRegisters::S0, dest, ARMAssembler::getOp2Byte(1));1152 m_assembler.bic _r(ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::getOp2Byte(1));1151 m_assembler.add(ARMRegisters::S0, dest, ARMAssembler::getOp2Byte(1)); 1152 m_assembler.bic(ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::getOp2Byte(1)); 1153 1153 1154 1154 ARMWord w = ARMAssembler::getOp2(0x80000000); 1155 1155 ASSERT(w != ARMAssembler::InvalidImmediate); 1156 m_assembler.cmp _r(ARMRegisters::S0, w);1156 m_assembler.cmp(ARMRegisters::S0, w); 1157 1157 return Jump(m_assembler.jmp(branchType == BranchIfTruncateFailed ? ARMAssembler::EQ : ARMAssembler::NE)); 1158 1158 } … … 1162 1162 truncateDoubleToUint32(src, dest); 1163 1163 1164 m_assembler.add _r(ARMRegisters::S0, dest, ARMAssembler::getOp2Byte(1));1165 m_assembler.bic _r(ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::getOp2Byte(1));1166 1167 m_assembler.cmp _r(ARMRegisters::S0, ARMAssembler::getOp2Byte(0));1164 m_assembler.add(ARMRegisters::S0, dest, ARMAssembler::getOp2Byte(1)); 1165 m_assembler.bic(ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::getOp2Byte(1)); 1166 1167 m_assembler.cmp(ARMRegisters::S0, ARMAssembler::getOp2Byte(0)); 1168 1168 return Jump(m_assembler.jmp(branchType == BranchIfTruncateFailed ? ARMAssembler::EQ : ARMAssembler::NE)); 1169 1169 } … … 1172 1172 void truncateDoubleToInt32(FPRegisterID src, RegisterID dest) 1173 1173 { 1174 m_assembler.vcvt_s32_f64 _r(ARMRegisters::SD0 << 1, src);1175 m_assembler.vmov_arm32 _r(dest, ARMRegisters::SD0 << 1);1174 m_assembler.vcvt_s32_f64(ARMRegisters::SD0 << 1, src); 1175 m_assembler.vmov_arm32(dest, ARMRegisters::SD0 << 1); 1176 1176 } 1177 1177 1178 1178 void truncateDoubleToUint32(FPRegisterID src, RegisterID dest) 1179 1179 { 1180 m_assembler.vcvt_u32_f64 _r(ARMRegisters::SD0 << 1, src);1181 m_assembler.vmov_arm32 _r(dest, ARMRegisters::SD0 << 1);1180 m_assembler.vcvt_u32_f64(ARMRegisters::SD0 << 1, src); 1181 m_assembler.vmov_arm32(dest, ARMRegisters::SD0 << 1); 1182 1182 } 1183 1183 … … 1188 1188 void branchConvertDoubleToInt32(FPRegisterID src, RegisterID dest, JumpList& failureCases, FPRegisterID fpTemp) 1189 1189 { 1190 m_assembler.vcvt_s32_f64 _r(ARMRegisters::SD0 << 1, src);1191 m_assembler.vmov_arm32 _r(dest, ARMRegisters::SD0 << 1);1190 m_assembler.vcvt_s32_f64(ARMRegisters::SD0 << 1, src); 1191 m_assembler.vmov_arm32(dest, ARMRegisters::SD0 << 1); 1192 1192 1193 1193 // Convert the integer result back to float & compare to the original value - if not equal or unordered (NaN) then jump. 1194 m_assembler.vcvt_f64_s32 _r(ARMRegisters::SD0, ARMRegisters::SD0 << 1);1194 m_assembler.vcvt_f64_s32(ARMRegisters::SD0, ARMRegisters::SD0 << 1); 1195 1195 failureCases.append(branchDouble(DoubleNotEqualOrUnordered, src, ARMRegisters::SD0)); 1196 1196 … … 1201 1201 Jump branchDoubleNonZero(FPRegisterID reg, FPRegisterID scratch) 1202 1202 { 1203 m_assembler.mov _r(ARMRegisters::S0, ARMAssembler::getOp2Byte(0));1203 m_assembler.mov(ARMRegisters::S0, ARMAssembler::getOp2Byte(0)); 1204 1204 convertInt32ToDouble(ARMRegisters::S0, scratch); 1205 1205 return branchDouble(DoubleNotEqual, reg, scratch); … … 1208 1208 Jump branchDoubleZeroOrNaN(FPRegisterID reg, FPRegisterID scratch) 1209 1209 { 1210 m_assembler.mov _r(ARMRegisters::S0, ARMAssembler::getOp2Byte(0));1210 m_assembler.mov(ARMRegisters::S0, ARMAssembler::getOp2Byte(0)); 1211 1211 convertInt32ToDouble(ARMRegisters::S0, scratch); 1212 1212 return branchDouble(DoubleEqualOrUnordered, reg, scratch);
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