Changeset 149634 in webkit
- Timestamp:
- May 6, 2013 1:28:31 PM (11 years ago)
- Location:
- trunk/Source/JavaScriptCore
- Files:
-
- 3 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/Source/JavaScriptCore/ChangeLog
r149633 r149634 1 2013-05-06 Julien Brianceau <jbrianceau@nds.com> 2 3 Misc bugfix and cleaning in sh4 base JIT. 4 https://bugs.webkit.org/show_bug.cgi?id=115627 5 6 Reviewed by Oliver Hunt. 7 8 Get rid of loadX(RegisterID r0, RegisterID src, RegisterID dest) functions. 9 Remove misplaced extuw() implementation from MacroAssemblerSH4. 10 Add movbRegMemr0 and movwRegMemr0 functions in SH4Assembler. 11 12 * assembler/MacroAssemblerSH4.h: 13 (JSC::MacroAssemblerSH4::add32): Skip operation when first operand is a zero immediate. 14 (JSC::MacroAssemblerSH4::sub32): Skip operation when first operand is a zero immediate. 15 (JSC::MacroAssemblerSH4::load32): Fix wrong usage of r0 register. 16 (JSC::MacroAssemblerSH4::load8Signed): Handle "base == r0" case. 17 (MacroAssemblerSH4): 18 (JSC::MacroAssemblerSH4::load16): Handle "base == r0" case. 19 (JSC::MacroAssemblerSH4::load16Unaligned): Use extuw() implementation from SH4Assembler. 20 (JSC::MacroAssemblerSH4::load16Signed): Cosmetic change. 21 (JSC::MacroAssemblerSH4::store8): Fix unhandled BaseIndex offset and handle (base == r0) case. 22 (JSC::MacroAssemblerSH4::store16): Fix unhandled BaseIndex offset and handle (base == r0) case. 23 (JSC::MacroAssemblerSH4::store32): 24 * assembler/SH4Assembler.h: 25 (JSC::SH4Assembler::movwRegMemr0): 26 (SH4Assembler): 27 (JSC::SH4Assembler::movbRegMemr0): 28 (JSC::SH4Assembler::placeConstantPoolBarrier): Cosmetic change. 29 (JSC::SH4Assembler::maxJumpReplacementSize): 30 (JSC::SH4Assembler::replaceWithJump): Correct branch range and save an opcode. 31 (JSC::SH4Assembler::printInstr): 32 1 33 2013-05-06 Anders Carlsson <andersca@apple.com> 2 34 -
trunk/Source/JavaScriptCore/assembler/MacroAssemblerSH4.h
r149403 r149634 111 111 void add32(TrustedImm32 imm, RegisterID dest) 112 112 { 113 if (!imm.m_value) 114 return; 115 113 116 if (m_assembler.isImmediate(imm.m_value)) { 114 117 m_assembler.addlImm8r(imm.m_value, dest); … … 131 134 void add32(TrustedImm32 imm, Address address) 132 135 { 136 if (!imm.m_value) 137 return; 138 133 139 RegisterID scr = claimScratch(); 134 140 load32(address, scr); … … 326 332 void sub32(TrustedImm32 imm, AbsoluteAddress address) 327 333 { 334 if (!imm.m_value) 335 return; 336 328 337 RegisterID result = claimScratch(); 329 338 RegisterID scratchReg = claimScratch(); … … 346 355 void add32(TrustedImm32 imm, AbsoluteAddress address) 347 356 { 357 if (!imm.m_value) 358 return; 359 348 360 RegisterID result = claimScratch(); 349 361 RegisterID scratchReg = claimScratch(); … … 394 406 void sub32(TrustedImm32 imm, RegisterID dest) 395 407 { 408 if (!imm.m_value) 409 return; 410 396 411 if (m_assembler.isImmediate(-imm.m_value)) { 397 412 m_assembler.addlImm8r(-imm.m_value, dest); … … 630 645 } 631 646 632 if ((dest == SH4Registers::r0) && (dest != base)) { 633 m_assembler.loadConstant((offset), dest); 634 m_assembler.movlR0mr(base, dest); 635 return; 636 } 637 638 RegisterID scr; 639 if (dest == base) 640 scr = claimScratch(); 641 else 642 scr = dest; 647 RegisterID scr = (dest == base) ? claimScratch() : dest; 648 643 649 m_assembler.loadConstant(offset, scr); 644 m_assembler.addlRegReg(base, scr); 645 m_assembler.movlMemReg(scr, dest); 650 if (base == SH4Registers::r0) 651 m_assembler.movlR0mr(scr, dest); 652 else { 653 m_assembler.addlRegReg(base, scr); 654 m_assembler.movlMemReg(scr, dest); 655 } 646 656 647 657 if (dest == base) … … 661 671 } 662 672 663 if (base != dest) { 664 m_assembler.loadConstant(offset, dest); 665 m_assembler.addlRegReg(base, dest); 666 m_assembler.movbMemReg(dest, dest); 667 return; 668 } 669 670 RegisterID scr = claimScratch(); 673 RegisterID scr = (dest == base) ? claimScratch() : dest; 674 671 675 m_assembler.loadConstant(offset, scr); 672 m_assembler.addlRegReg(base, scr); 673 m_assembler.movbMemReg(scr, dest); 674 releaseScratch(scr); 676 if (base == SH4Registers::r0) 677 m_assembler.movbR0mr(scr, dest); 678 else { 679 m_assembler.addlRegReg(base, scr); 680 m_assembler.movbMemReg(scr, dest); 681 } 682 683 if (dest == base) 684 releaseScratch(scr); 675 685 } 676 686 … … 681 691 } 682 692 683 void load32(RegisterID r0, RegisterID src, RegisterID dst)684 {685 ASSERT(r0 == SH4Registers::r0);686 m_assembler.movlR0mr(src, dst);687 }688 689 693 void load32(RegisterID src, RegisterID dst) 690 694 { … … 696 700 if (!address.offset) { 697 701 m_assembler.movwMemReg(address.base, dest); 698 extuw(dest, dest);702 m_assembler.extuw(dest, dest); 699 703 return; 700 704 } … … 702 706 if ((address.offset > 0) && (address.offset <= 30) && (dest == SH4Registers::r0)) { 703 707 m_assembler.movwMemReg(address.offset >> 1, address.base, dest); 704 extuw(dest, dest); 705 return; 706 } 707 708 if (address.base != dest) { 709 m_assembler.loadConstant(address.offset, dest); 710 m_assembler.addlRegReg(address.base, dest); 711 m_assembler.movwMemReg(dest, dest); 712 extuw(dest, dest); 713 return; 714 } 715 716 RegisterID scr = claimScratch(); 708 m_assembler.extuw(dest, dest); 709 return; 710 } 711 712 RegisterID scr = (dest == address.base) ? claimScratch() : dest; 713 717 714 m_assembler.loadConstant(address.offset, scr); 718 m_assembler.addlRegReg(address.base, scr); 719 m_assembler.movwMemReg(scr, dest); 720 extuw(dest, dest); 721 releaseScratch(scr); 715 if (address.base == SH4Registers::r0) 716 m_assembler.movwR0mr(scr, dest); 717 else { 718 m_assembler.addlRegReg(address.base, scr); 719 m_assembler.movwMemReg(scr, dest); 720 } 721 m_assembler.extuw(dest, dest); 722 723 if (dest == address.base) 724 releaseScratch(scr); 722 725 } 723 726 724 727 void load16Unaligned(BaseIndex address, RegisterID dest) 725 728 { 726 727 729 RegisterID scr = claimScratch(); 728 730 RegisterID scr1 = claimScratch(); … … 748 750 { 749 751 m_assembler.movwMemReg(src, dest); 750 extuw(dest, dest);752 m_assembler.extuw(dest, dest); 751 753 } 752 754 … … 756 758 } 757 759 758 void load16(RegisterID r0, RegisterID src, RegisterID dest)759 {760 ASSERT(r0 == SH4Registers::r0);761 m_assembler.movwR0mr(src, dest);762 extuw(dest, dest);763 }764 765 void load16Signed(RegisterID r0, RegisterID src, RegisterID dest)766 {767 ASSERT(r0 == SH4Registers::r0);768 m_assembler.movwR0mr(src, dest);769 }770 771 760 void load16(BaseIndex address, RegisterID dest) 761 { 762 load16Signed(address, dest); 763 m_assembler.extuw(dest, dest); 764 } 765 766 void load16Signed(BaseIndex address, RegisterID dest) 772 767 { 773 768 RegisterID scr = claimScratch(); … … 778 773 if (address.offset) 779 774 add32(TrustedImm32(address.offset), scr); 775 780 776 if (address.base == SH4Registers::r0) 781 load16(address.base, scr, dest); 782 else { 783 add32(address.base, scr); 784 load16(scr, dest); 785 } 786 787 releaseScratch(scr); 788 } 789 790 void load16Signed(BaseIndex address, RegisterID dest) 791 { 792 RegisterID scr = claimScratch(); 793 794 move(address.index, scr); 795 lshift32(TrustedImm32(address.scale), scr); 796 797 if (address.offset) 798 add32(TrustedImm32(address.offset), scr); 799 if (address.base == SH4Registers::r0) 800 load16Signed(address.base, scr, dest); 777 m_assembler.movwR0mr(scr, dest); 801 778 else { 802 779 add32(address.base, scr); … … 813 790 move(address.index, scr); 814 791 lshift32(TrustedImm32(address.scale), scr); 815 add32(address.base, scr); 816 817 m_assembler.movbRegMem(src, scr); 792 add32(TrustedImm32(address.offset), scr); 793 794 if (address.base == SH4Registers::r0) 795 m_assembler.movbRegMemr0(src, scr); 796 else { 797 add32(address.base, scr); 798 m_assembler.movbRegMem(src, scr); 799 } 818 800 819 801 releaseScratch(scr); … … 826 808 move(address.index, scr); 827 809 lshift32(TrustedImm32(address.scale), scr); 828 add32(address.base, scr); 829 830 m_assembler.movwRegMem(src, scr); 810 add32(TrustedImm32(address.offset), scr); 811 812 if (address.base == SH4Registers::r0) 813 m_assembler.movwRegMemr0(src, scr); 814 else { 815 add32(address.base, scr); 816 m_assembler.movwRegMem(src, scr); 817 } 831 818 832 819 releaseScratch(scr); … … 835 822 void store32(RegisterID src, ImplicitAddress address) 836 823 { 837 RegisterID scr = claimScratch(); 838 store32(src, address.offset, address.base, scr); 839 releaseScratch(scr); 840 } 841 842 void store32(RegisterID src, int offset, RegisterID base, RegisterID scr) 843 { 844 if (!offset) { 845 m_assembler.movlRegMem(src, base); 846 return; 847 } 848 849 if ((offset >= 0) && (offset < 64)) { 850 m_assembler.movlRegMem(src, offset >> 2, base); 851 return; 852 } 853 854 m_assembler.loadConstant(offset, scr); 855 if (scr == SH4Registers::r0) { 856 m_assembler.movlRegMemr0(src, base); 857 return; 858 } 859 860 m_assembler.addlRegReg(base, scr); 861 m_assembler.movlRegMem(src, scr); 862 } 863 864 void store32(RegisterID src, RegisterID offset, RegisterID base) 865 { 866 ASSERT(offset == SH4Registers::r0); 867 m_assembler.movlRegMemr0(src, base); 824 if (!address.offset) { 825 m_assembler.movlRegMem(src, address.base); 826 return; 827 } 828 829 if ((address.offset >= 0) && (address.offset < 64)) { 830 m_assembler.movlRegMem(src, address.offset >> 2, address.base); 831 return; 832 } 833 834 RegisterID scr = claimScratch(); 835 m_assembler.loadConstant(address.offset, scr); 836 if (address.base == SH4Registers::r0) 837 m_assembler.movlRegMemr0(src, scr); 838 else { 839 m_assembler.addlRegReg(address.base, scr); 840 m_assembler.movlRegMem(src, scr); 841 } 842 releaseScratch(scr); 868 843 } 869 844 … … 876 851 { 877 852 RegisterID scr = claimScratch(); 878 RegisterID scr1 = claimScratch();879 853 m_assembler.loadConstant(imm.m_value, scr); 880 store32(scr, address.offset, address.base, scr1); 881 releaseScratch(scr); 882 releaseScratch(scr1); 854 store32(scr, address); 855 releaseScratch(scr); 883 856 } 884 857 … … 1574 1547 { 1575 1548 m_assembler.loadConstant(imm.asIntptr(), dest); 1576 }1577 1578 void extuw(RegisterID src, RegisterID dst)1579 {1580 m_assembler.extuw(src, dst);1581 1549 } 1582 1550 -
trunk/Source/JavaScriptCore/assembler/SH4Assembler.h
r149403 r149634 116 116 MOVL_READ_OFFRM_OPCODE = 0x5000, 117 117 MOVW_WRITE_RN_OPCODE = 0x2001, 118 MOVW_WRITE_R0RN_OPCODE = 0x0005, 118 119 MOVW_READ_RM_OPCODE = 0x6001, 119 120 MOVW_READ_R0RM_OPCODE = 0x000d, … … 1061 1062 } 1062 1063 1064 void movwRegMemr0(RegisterID src, RegisterID dst) 1065 { 1066 uint16_t opc = getOpcodeGroup1(MOVW_WRITE_R0RN_OPCODE, dst, src); 1067 oneShortOp(opc); 1068 } 1069 1063 1070 void movlRegMem(RegisterID src, int offset, RegisterID base) 1064 1071 { … … 1124 1131 { 1125 1132 uint16_t opc = getOpcodeGroup1(MOVB_READ_RM_OPCODE, dst, src); 1133 oneShortOp(opc); 1134 } 1135 1136 void movbRegMemr0(RegisterID src, RegisterID dst) 1137 { 1138 uint16_t opc = getOpcodeGroup1(MOVB_WRITE_R0RN_OPCODE, dst, src); 1126 1139 oneShortOp(opc); 1127 1140 } … … 1381 1394 static SH4Buffer::TwoShorts placeConstantPoolBarrier(int offset) 1382 1395 { 1383 ASSERT(((offset >> 1) <= 2047) && ((offset >> 1) >= -2048));1396 ASSERT(((offset >> 1) <= 2047) && ((offset >> 1) >= -2048)); 1384 1397 1385 1398 SH4Buffer::TwoShorts m_barrier; … … 1475 1488 static ptrdiff_t maxJumpReplacementSize() 1476 1489 { 1477 return sizeof(SH4Word) * 7;1490 return sizeof(SH4Word) * 6; 1478 1491 } 1479 1492 … … 1484 1497 int nbinst = 0; 1485 1498 1486 if ((difference >= - 2048) && (difference <= 2047)) {1499 if ((difference >= -4096) && (difference <= 4094)) { 1487 1500 instruction[0] = getOpcodeGroup6(BRA_OPCODE, difference >> 1); 1488 1501 instruction[1] = NOP_OPCODE; … … 1491 1504 } 1492 1505 1493 if (reinterpret_cast<unsigned>(instruction) & 3)1494 instruction[nbinst++] = NOP_OPCODE;1495 1496 1506 instruction[nbinst++] = getOpcodeGroup3(MOVL_READ_OFFPC_OPCODE, scratchReg2, 1); 1497 1507 instruction[nbinst++] = getOpcodeGroup2(JMP_OPCODE, scratchReg2); 1498 1508 instruction[nbinst++] = NOP_OPCODE; 1499 instruction[nbinst++] = NOP_OPCODE; 1509 1510 if (!(reinterpret_cast<unsigned>(instruction) & 3)) 1511 instruction[nbinst++] = NOP_OPCODE; 1512 1500 1513 instruction[nbinst++] = reinterpret_cast<unsigned>(to) & 0xffff; 1501 1514 instruction[nbinst++] = reinterpret_cast<unsigned>(to) >> 16; … … 1949 1962 format = " MOV.W @(R0, R%d), R%d\n"; 1950 1963 break; 1964 case MOVW_WRITE_R0RN_OPCODE: 1965 format = " MOV.W R%d, @(R0, R%d)\n"; 1966 break; 1951 1967 case EXTUB_OPCODE: 1952 1968 format = " EXTU.B R%d, R%d\n";
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