Changeset 172746 in webkit

Timestamp:

Aug 19, 2014 12:14:30 AM (10 years ago)

Author:

Csaba Osztrogonác

Message:

REGRESSION(r163179): It broke the build on ARM Thumb2 with GCC
​https://bugs.webkit.org/show_bug.cgi?id=136028

Patch by Michael Saboff <​msaboff@apple.com> on 2014-08-19
Reviewed by Oliver Hunt.

Added back ARMv7 conditionals around three op addp and subp since ARM Thumb2 spec says that
the behavior for those ops are undefined. This was originally done in changeset 163179.

• llint/LowLevelInterpreter32_64.asm:

Location:

trunk/Source/JavaScriptCore

Files:

• ChangeLog (modified) (1 diff)
• llint/LowLevelInterpreter32_64.asm (modified) (8 diffs)

trunk/Source/JavaScriptCore/ChangeLog

@@ +1 @@
+2014-08-19  Michael Saboff  <msaboff@apple.com>
+
+        REGRESSION(r163179): It broke the build on ARM Thumb2 with GCC
+        https://bugs.webkit.org/show_bug.cgi?id=136028
+
+        Reviewed by Oliver Hunt.
+
+        Added back ARMv7 conditionals around three op addp and subp since ARM Thumb2 spec says that
+        the behavior for those ops are undefined.  This was originally done in changeset 163179.
+
+        * llint/LowLevelInterpreter32_64.asm:
+
 2014-08-18  Commit Queue  <commit-queue@webkit.org>
 

trunk/Source/JavaScriptCore/llint/LowLevelInterpreter32_64.asm

@@ -204 +204 @@
     end
 
-    vmEntryRecord(cfr, sp)
+    if ARMv7
+        vmEntryRecord(cfr, temp1)
+        move temp1, sp
+    else
+        vmEntryRecord(cfr, sp)
+    end
 
     storep vm, VMEntryRecord::m_vm[sp]
@@ -220 +225 @@
         addp CallFrameAlignSlots * SlotSize, sp, temp1
         clrbp temp1, StackAlignmentMask, temp1
-        subp temp1, CallFrameAlignSlots * SlotSize, sp
+        if ARMv7
+            subp temp1, CallFrameAlignSlots * SlotSize, temp1
+            move temp1, sp
+        else
+            subp temp1, CallFrameAlignSlots * SlotSize, sp
+        end
     end
 
@@ -253 +263 @@
     cCall2(_llint_throw_stack_overflow_error, vm, protoCallFrame)
 
-    vmEntryRecord(cfr, sp)
+    if ARMv7
+        vmEntryRecord(cfr, temp1)
+        move temp1, sp
+    else
+        vmEntryRecord(cfr, sp)
+    end
 
     loadp VMEntryRecord::m_vm[sp], temp3
@@ -261 +276 @@
     storep temp4, VM::topVMEntryFrame[temp3]
 
-    subp cfr, CalleeRegisterSaveSize, sp
+    if ARMv7
+        subp cfr, CalleeRegisterSaveSize, temp3
+        move temp3, sp
+    else
+        subp cfr, CalleeRegisterSaveSize, sp
+    end
 
     popCalleeSaves()
@@ -309 +329 @@
     makeCall(entry, temp1, temp2)
 
-    vmEntryRecord(cfr, sp)
+    if ARMv7
+        vmEntryRecord(cfr, temp1)
+        move temp1, sp
+    else
+        vmEntryRecord(cfr, sp)
+    end
 
     loadp VMEntryRecord::m_vm[sp], temp3
@@ -317 +342 @@
     storep temp4, VM::topVMEntryFrame[temp3]
 
-    subp cfr, CalleeRegisterSaveSize, sp
+    if ARMv7
+        subp cfr, CalleeRegisterSaveSize, temp3
+        move temp3, sp
+    else
+        subp cfr, CalleeRegisterSaveSize, sp
+    end
 
     popCalleeSaves()
@@ -373 +403 @@
     loadp CallerFrame + PayloadOffset[cfr], cfr
 
-    vmEntryRecord(cfr, sp)
+    if ARMv7
+        vmEntryRecord(cfr, t3)
+        move t3, sp
+    else
+        vmEntryRecord(cfr, sp)
+    end
 
     loadp VMEntryRecord::m_vm[sp], t3
@@ -381 +416 @@
     storep t5, VM::topVMEntryFrame[t3]
 
-    subp cfr, CalleeRegisterSaveSize, sp
+    if ARMv7
+        subp cfr, CalleeRegisterSaveSize, t3
+        move t3, sp
+    else
+        subp cfr, CalleeRegisterSaveSize, sp
+    end
 
     popCalleeSaves()