Changeset 196736 in webkit


Ignore:
Timestamp:
Feb 17, 2016 5:38:40 PM (8 years ago)
Author:
commit-queue@webkit.org
Message:

[JSC] ARM64: Support the immediate format used for bit operations in Air
https://bugs.webkit.org/show_bug.cgi?id=154327

Patch by Benjamin Poulain <bpoulain@apple.com> on 2016-02-17
Reviewed by Filip Pizlo.

ARM64 supports a pretty rich form of immediates for bit operation.
There are two formats used to encode repeating patterns and common
input in a dense form.

In this patch, I add 2 new type of Arg: BitImm32 and BitImm64.
Those represents the valid immediate forms for bit operation.
On x86, any 32bits value is valid. On ARM64, all the encoding
form are tried and the immediate is used when possible.

The arg type Imm64 is renamed to BigImm to better represent what
it is: an immediate that does not fit into Imm.

  • assembler/ARM64Assembler.h:

(JSC::LogicalImmediate::create32): Deleted.
(JSC::LogicalImmediate::create64): Deleted.
(JSC::LogicalImmediate::value): Deleted.
(JSC::LogicalImmediate::isValid): Deleted.
(JSC::LogicalImmediate::is64bit): Deleted.
(JSC::LogicalImmediate::LogicalImmediate): Deleted.
(JSC::LogicalImmediate::mask): Deleted.
(JSC::LogicalImmediate::partialHSB): Deleted.
(JSC::LogicalImmediate::highestSetBit): Deleted.
(JSC::LogicalImmediate::findBitRange): Deleted.
(JSC::LogicalImmediate::encodeLogicalImmediate): Deleted.

  • assembler/AssemblerCommon.h:

(JSC::ARM64LogicalImmediate::create32):
(JSC::ARM64LogicalImmediate::create64):
(JSC::ARM64LogicalImmediate::value):
(JSC::ARM64LogicalImmediate::isValid):
(JSC::ARM64LogicalImmediate::is64bit):
(JSC::ARM64LogicalImmediate::ARM64LogicalImmediate):
(JSC::ARM64LogicalImmediate::mask):
(JSC::ARM64LogicalImmediate::partialHSB):
(JSC::ARM64LogicalImmediate::highestSetBit):
(JSC::ARM64LogicalImmediate::findBitRange):
(JSC::ARM64LogicalImmediate::encodeLogicalImmediate):

  • assembler/MacroAssemblerARM64.h:

(JSC::MacroAssemblerARM64::and64):
(JSC::MacroAssemblerARM64::or64):
(JSC::MacroAssemblerARM64::xor64):

  • b3/B3LowerToAir.cpp:

(JSC::B3::Air::LowerToAir::bitImm):
(JSC::B3::Air::LowerToAir::bitImm64):
(JSC::B3::Air::LowerToAir::appendBinOp):

  • b3/air/AirArg.cpp:

(JSC::B3::Air::Arg::dump):
(WTF::printInternal):

  • b3/air/AirArg.h:

(JSC::B3::Air::Arg::bitImm):
(JSC::B3::Air::Arg::bitImm64):
(JSC::B3::Air::Arg::isBitImm):
(JSC::B3::Air::Arg::isBitImm64):
(JSC::B3::Air::Arg::isSomeImm):
(JSC::B3::Air::Arg::value):
(JSC::B3::Air::Arg::isGP):
(JSC::B3::Air::Arg::isFP):
(JSC::B3::Air::Arg::hasType):
(JSC::B3::Air::Arg::isValidBitImmForm):
(JSC::B3::Air::Arg::isValidBitImm64Form):
(JSC::B3::Air::Arg::isValidForm):
(JSC::B3::Air::Arg::asTrustedImm32):
(JSC::B3::Air::Arg::asTrustedImm64):

  • b3/air/AirOpcode.opcodes:
  • b3/air/opcode_generator.rb:
Location:
trunk/Source/JavaScriptCore
Files:
14 edited

Legend:

Unmodified
Added
Removed
  • trunk/Source/JavaScriptCore/ChangeLog

    r196734 r196736  
     12016-02-17  Benjamin Poulain  <bpoulain@apple.com>
     2
     3        [JSC] ARM64: Support the immediate format used for bit operations in Air
     4        https://bugs.webkit.org/show_bug.cgi?id=154327
     5
     6        Reviewed by Filip Pizlo.
     7
     8        ARM64 supports a pretty rich form of immediates for bit operation.
     9        There are two formats used to encode repeating patterns and common
     10        input in a dense form.
     11
     12        In this patch, I add 2 new type of Arg: BitImm32 and BitImm64.
     13        Those represents the valid immediate forms for bit operation.
     14        On x86, any 32bits value is valid. On ARM64, all the encoding
     15        form are tried and the immediate is used when possible.
     16
     17        The arg type Imm64 is renamed to BigImm to better represent what
     18        it is: an immediate that does not fit into Imm.
     19
     20        * assembler/ARM64Assembler.h:
     21        (JSC::LogicalImmediate::create32): Deleted.
     22        (JSC::LogicalImmediate::create64): Deleted.
     23        (JSC::LogicalImmediate::value): Deleted.
     24        (JSC::LogicalImmediate::isValid): Deleted.
     25        (JSC::LogicalImmediate::is64bit): Deleted.
     26        (JSC::LogicalImmediate::LogicalImmediate): Deleted.
     27        (JSC::LogicalImmediate::mask): Deleted.
     28        (JSC::LogicalImmediate::partialHSB): Deleted.
     29        (JSC::LogicalImmediate::highestSetBit): Deleted.
     30        (JSC::LogicalImmediate::findBitRange): Deleted.
     31        (JSC::LogicalImmediate::encodeLogicalImmediate): Deleted.
     32        * assembler/AssemblerCommon.h:
     33        (JSC::ARM64LogicalImmediate::create32):
     34        (JSC::ARM64LogicalImmediate::create64):
     35        (JSC::ARM64LogicalImmediate::value):
     36        (JSC::ARM64LogicalImmediate::isValid):
     37        (JSC::ARM64LogicalImmediate::is64bit):
     38        (JSC::ARM64LogicalImmediate::ARM64LogicalImmediate):
     39        (JSC::ARM64LogicalImmediate::mask):
     40        (JSC::ARM64LogicalImmediate::partialHSB):
     41        (JSC::ARM64LogicalImmediate::highestSetBit):
     42        (JSC::ARM64LogicalImmediate::findBitRange):
     43        (JSC::ARM64LogicalImmediate::encodeLogicalImmediate):
     44        * assembler/MacroAssemblerARM64.h:
     45        (JSC::MacroAssemblerARM64::and64):
     46        (JSC::MacroAssemblerARM64::or64):
     47        (JSC::MacroAssemblerARM64::xor64):
     48        * b3/B3LowerToAir.cpp:
     49        (JSC::B3::Air::LowerToAir::bitImm):
     50        (JSC::B3::Air::LowerToAir::bitImm64):
     51        (JSC::B3::Air::LowerToAir::appendBinOp):
     52        * b3/air/AirArg.cpp:
     53        (JSC::B3::Air::Arg::dump):
     54        (WTF::printInternal):
     55        * b3/air/AirArg.h:
     56        (JSC::B3::Air::Arg::bitImm):
     57        (JSC::B3::Air::Arg::bitImm64):
     58        (JSC::B3::Air::Arg::isBitImm):
     59        (JSC::B3::Air::Arg::isBitImm64):
     60        (JSC::B3::Air::Arg::isSomeImm):
     61        (JSC::B3::Air::Arg::value):
     62        (JSC::B3::Air::Arg::isGP):
     63        (JSC::B3::Air::Arg::isFP):
     64        (JSC::B3::Air::Arg::hasType):
     65        (JSC::B3::Air::Arg::isValidBitImmForm):
     66        (JSC::B3::Air::Arg::isValidBitImm64Form):
     67        (JSC::B3::Air::Arg::isValidForm):
     68        (JSC::B3::Air::Arg::asTrustedImm32):
     69        (JSC::B3::Air::Arg::asTrustedImm64):
     70        * b3/air/AirOpcode.opcodes:
     71        * b3/air/opcode_generator.rb:
     72
    1732016-02-17  Keith Miller  <keith_miller@apple.com>
    274
  • trunk/Source/JavaScriptCore/assembler/ARM64Assembler.h

    r195578 r196736  
    148148};
    149149
    150 class LogicalImmediate {
    151 public:
    152     static LogicalImmediate create32(uint32_t value)
    153     {
    154         // Check for 0, -1 - these cannot be encoded.
    155         if (!value || !~value)
    156             return InvalidLogicalImmediate;
    157 
    158         // First look for a 32-bit pattern, then for repeating 16-bit
    159         // patterns, 8-bit, 4-bit, and finally 2-bit.
    160 
    161         unsigned hsb, lsb;
    162         bool inverted;
    163         if (findBitRange<32>(value, hsb, lsb, inverted))
    164             return encodeLogicalImmediate<32>(hsb, lsb, inverted);
    165 
    166         if ((value & 0xffff) != (value >> 16))
    167             return InvalidLogicalImmediate;
    168         value &= 0xffff;
    169 
    170         if (findBitRange<16>(value, hsb, lsb, inverted))
    171             return encodeLogicalImmediate<16>(hsb, lsb, inverted);
    172 
    173         if ((value & 0xff) != (value >> 8))
    174             return InvalidLogicalImmediate;
    175         value &= 0xff;
    176 
    177         if (findBitRange<8>(value, hsb, lsb, inverted))
    178             return encodeLogicalImmediate<8>(hsb, lsb, inverted);
    179 
    180         if ((value & 0xf) != (value >> 4))
    181             return InvalidLogicalImmediate;
    182         value &= 0xf;
    183 
    184         if (findBitRange<4>(value, hsb, lsb, inverted))
    185             return encodeLogicalImmediate<4>(hsb, lsb, inverted);
    186 
    187         if ((value & 0x3) != (value >> 2))
    188             return InvalidLogicalImmediate;
    189         value &= 0x3;
    190 
    191         if (findBitRange<2>(value, hsb, lsb, inverted))
    192             return encodeLogicalImmediate<2>(hsb, lsb, inverted);
    193 
    194         return InvalidLogicalImmediate;
    195     }
    196 
    197     static LogicalImmediate create64(uint64_t value)
    198     {
    199         // Check for 0, -1 - these cannot be encoded.
    200         if (!value || !~value)
    201             return InvalidLogicalImmediate;
    202 
    203         // Look for a contiguous bit range.
    204         unsigned hsb, lsb;
    205         bool inverted;
    206         if (findBitRange<64>(value, hsb, lsb, inverted))
    207             return encodeLogicalImmediate<64>(hsb, lsb, inverted);
    208 
    209         // If the high & low 32 bits are equal, we can try for a 32-bit (or narrower) pattern.
    210         if (static_cast<uint32_t>(value) == static_cast<uint32_t>(value >> 32))
    211             return create32(static_cast<uint32_t>(value));
    212         return InvalidLogicalImmediate;
    213     }
    214 
    215     int value() const
    216     {
    217         ASSERT(isValid());
    218         return m_value;
    219     }
    220 
    221     bool isValid() const
    222     {
    223         return m_value != InvalidLogicalImmediate;
    224     }
    225 
    226     bool is64bit() const
    227     {
    228         return m_value & (1 << 12);
    229     }
    230 
    231 private:
    232     LogicalImmediate(int value)
    233         : m_value(value)
    234     {
    235     }
    236 
    237     // Generate a mask with bits in the range hsb..0 set, for example:
    238     //   hsb:63 = 0xffffffffffffffff
    239     //   hsb:42 = 0x000007ffffffffff
    240     //   hsb: 0 = 0x0000000000000001
    241     static uint64_t mask(unsigned hsb)
    242     {
    243         ASSERT(hsb < 64);
    244         return 0xffffffffffffffffull >> (63 - hsb);
    245     }
    246 
    247     template<unsigned N>
    248     static void partialHSB(uint64_t& value, unsigned&result)
    249     {
    250         if (value & (0xffffffffffffffffull << N)) {
    251             result += N;
    252             value >>= N;
    253         }
    254     }
    255 
    256     // Find the bit number of the highest bit set in a non-zero value, for example:
    257     //   0x8080808080808080 = hsb:63
    258     //   0x0000000000000001 = hsb: 0
    259     //   0x000007ffffe00000 = hsb:42
    260     static unsigned highestSetBit(uint64_t value)
    261     {
    262         ASSERT(value);
    263         unsigned hsb = 0;
    264         partialHSB<32>(value, hsb);
    265         partialHSB<16>(value, hsb);
    266         partialHSB<8>(value, hsb);
    267         partialHSB<4>(value, hsb);
    268         partialHSB<2>(value, hsb);
    269         partialHSB<1>(value, hsb);
    270         return hsb;
    271     }
    272 
    273     // This function takes a value and a bit width, where value obeys the following constraints:
    274     //   * bits outside of the width of the value must be zero.
    275     //   * bits within the width of value must neither be all clear or all set.
    276     // The input is inspected to detect values that consist of either two or three contiguous
    277     // ranges of bits. The output range hsb..lsb will describe the second range of the value.
    278     // if the range is set, inverted will be false, and if the range is clear, inverted will
    279     // be true. For example (with width 8):
    280     //   00001111 = hsb:3, lsb:0, inverted:false
    281     //   11110000 = hsb:3, lsb:0, inverted:true
    282     //   00111100 = hsb:5, lsb:2, inverted:false
    283     //   11000011 = hsb:5, lsb:2, inverted:true
    284     template<unsigned width>
    285     static bool findBitRange(uint64_t value, unsigned& hsb, unsigned& lsb, bool& inverted)
    286     {
    287         ASSERT(value & mask(width - 1));
    288         ASSERT(value != mask(width - 1));
    289         ASSERT(!(value & ~mask(width - 1)));
    290 
    291         // Detect cases where the top bit is set; if so, flip all the bits & set invert.
    292         // This halves the number of patterns we need to look for.
    293         const uint64_t msb = 1ull << (width - 1);
    294         if ((inverted = (value & msb)))
    295             value ^= mask(width - 1);
    296 
    297         // Find the highest set bit in value, generate a corresponding mask & flip all
    298         // bits under it.
    299         hsb = highestSetBit(value);
    300         value ^= mask(hsb);
    301         if (!value) {
    302             // If this cleared the value, then the range hsb..0 was all set.
    303             lsb = 0;
    304             return true;
    305         }
    306 
    307         // Try making one more mask, and flipping the bits!
    308         lsb = highestSetBit(value);
    309         value ^= mask(lsb);
    310         if (!value) {
    311             // Success - but lsb actually points to the hsb of a third range - add one
    312             // to get to the lsb of the mid range.
    313             ++lsb;
    314             return true;
    315         }
    316 
    317         return false;
    318     }
    319 
    320     // Encodes the set of immN:immr:imms fields found in a logical immediate.
    321     template<unsigned width>
    322     static int encodeLogicalImmediate(unsigned hsb, unsigned lsb, bool inverted)
    323     {
    324         // Check width is a power of 2!
    325         ASSERT(!(width & (width -1)));
    326         ASSERT(width <= 64 && width >= 2);
    327         ASSERT(hsb >= lsb);
    328         ASSERT(hsb < width);
    329 
    330         int immN = 0;
    331         int imms = 0;
    332         int immr = 0;
    333 
    334         // For 64-bit values this is easy - just set immN to true, and imms just
    335         // contains the bit number of the highest set bit of the set range. For
    336         // values with narrower widths, these are encoded by a leading set of
    337         // one bits, followed by a zero bit, followed by the remaining set of bits
    338         // being the high bit of the range. For a 32-bit immediate there are no
    339         // leading one bits, just a zero followed by a five bit number. For a
    340         // 16-bit immediate there is one one bit, a zero bit, and then a four bit
    341         // bit-position, etc.
    342         if (width == 64)
    343             immN = 1;
    344         else
    345             imms = 63 & ~(width + width - 1);
    346 
    347         if (inverted) {
    348             // if width is 64 & hsb is 62, then we have a value something like:
    349             //   0x80000000ffffffff (in this case with lsb 32).
    350             // The ror should be by 1, imms (effectively set width minus 1) is
    351             // 32. Set width is full width minus cleared width.
    352             immr = (width - 1) - hsb;
    353             imms |= (width - ((hsb - lsb) + 1)) - 1;
    354         } else {
    355             // if width is 64 & hsb is 62, then we have a value something like:
    356             //   0x7fffffff00000000 (in this case with lsb 32).
    357             // The value is effectively rol'ed by lsb, which is equivalent to
    358             // a ror by width - lsb (or 0, in the case where lsb is 0). imms
    359             // is hsb - lsb.
    360             immr = (width - lsb) & (width - 1);
    361             imms |= hsb - lsb;
    362         }
    363 
    364         return immN << 12 | immr << 6 | imms;
    365     }
    366 
    367     static const int InvalidLogicalImmediate = -1;
    368 
    369     int m_value;
    370 };
     150typedef ARM64LogicalImmediate LogicalImmediate;
    371151
    372152inline uint16_t getHalfword(uint64_t value, int which)
  • trunk/Source/JavaScriptCore/assembler/AssemblerCommon.h

    r195578 r196736  
    6767}
    6868
     69class ARM64LogicalImmediate {
     70public:
     71    static ARM64LogicalImmediate create32(uint32_t value)
     72    {
     73        // Check for 0, -1 - these cannot be encoded.
     74        if (!value || !~value)
     75            return InvalidLogicalImmediate;
     76
     77        // First look for a 32-bit pattern, then for repeating 16-bit
     78        // patterns, 8-bit, 4-bit, and finally 2-bit.
     79
     80        unsigned hsb, lsb;
     81        bool inverted;
     82        if (findBitRange<32>(value, hsb, lsb, inverted))
     83            return encodeLogicalImmediate<32>(hsb, lsb, inverted);
     84
     85        if ((value & 0xffff) != (value >> 16))
     86            return InvalidLogicalImmediate;
     87        value &= 0xffff;
     88
     89        if (findBitRange<16>(value, hsb, lsb, inverted))
     90            return encodeLogicalImmediate<16>(hsb, lsb, inverted);
     91
     92        if ((value & 0xff) != (value >> 8))
     93            return InvalidLogicalImmediate;
     94        value &= 0xff;
     95
     96        if (findBitRange<8>(value, hsb, lsb, inverted))
     97            return encodeLogicalImmediate<8>(hsb, lsb, inverted);
     98
     99        if ((value & 0xf) != (value >> 4))
     100            return InvalidLogicalImmediate;
     101        value &= 0xf;
     102
     103        if (findBitRange<4>(value, hsb, lsb, inverted))
     104            return encodeLogicalImmediate<4>(hsb, lsb, inverted);
     105
     106        if ((value & 0x3) != (value >> 2))
     107            return InvalidLogicalImmediate;
     108        value &= 0x3;
     109
     110        if (findBitRange<2>(value, hsb, lsb, inverted))
     111            return encodeLogicalImmediate<2>(hsb, lsb, inverted);
     112
     113        return InvalidLogicalImmediate;
     114    }
     115
     116    static ARM64LogicalImmediate create64(uint64_t value)
     117    {
     118        // Check for 0, -1 - these cannot be encoded.
     119        if (!value || !~value)
     120            return InvalidLogicalImmediate;
     121
     122        // Look for a contiguous bit range.
     123        unsigned hsb, lsb;
     124        bool inverted;
     125        if (findBitRange<64>(value, hsb, lsb, inverted))
     126            return encodeLogicalImmediate<64>(hsb, lsb, inverted);
     127
     128        // If the high & low 32 bits are equal, we can try for a 32-bit (or narrower) pattern.
     129        if (static_cast<uint32_t>(value) == static_cast<uint32_t>(value >> 32))
     130            return create32(static_cast<uint32_t>(value));
     131        return InvalidLogicalImmediate;
     132    }
     133
     134    int value() const
     135    {
     136        ASSERT(isValid());
     137        return m_value;
     138    }
     139
     140    bool isValid() const
     141    {
     142        return m_value != InvalidLogicalImmediate;
     143    }
     144
     145    bool is64bit() const
     146    {
     147        return m_value & (1 << 12);
     148    }
     149
     150private:
     151    ARM64LogicalImmediate(int value)
     152        : m_value(value)
     153    {
     154    }
     155
     156    // Generate a mask with bits in the range hsb..0 set, for example:
     157    //   hsb:63 = 0xffffffffffffffff
     158    //   hsb:42 = 0x000007ffffffffff
     159    //   hsb: 0 = 0x0000000000000001
     160    static uint64_t mask(unsigned hsb)
     161    {
     162        ASSERT(hsb < 64);
     163        return 0xffffffffffffffffull >> (63 - hsb);
     164    }
     165
     166    template<unsigned N>
     167    static void partialHSB(uint64_t& value, unsigned&result)
     168    {
     169        if (value & (0xffffffffffffffffull << N)) {
     170            result += N;
     171            value >>= N;
     172        }
     173    }
     174
     175    // Find the bit number of the highest bit set in a non-zero value, for example:
     176    //   0x8080808080808080 = hsb:63
     177    //   0x0000000000000001 = hsb: 0
     178    //   0x000007ffffe00000 = hsb:42
     179    static unsigned highestSetBit(uint64_t value)
     180    {
     181        ASSERT(value);
     182        unsigned hsb = 0;
     183        partialHSB<32>(value, hsb);
     184        partialHSB<16>(value, hsb);
     185        partialHSB<8>(value, hsb);
     186        partialHSB<4>(value, hsb);
     187        partialHSB<2>(value, hsb);
     188        partialHSB<1>(value, hsb);
     189        return hsb;
     190    }
     191
     192    // This function takes a value and a bit width, where value obeys the following constraints:
     193    //   * bits outside of the width of the value must be zero.
     194    //   * bits within the width of value must neither be all clear or all set.
     195    // The input is inspected to detect values that consist of either two or three contiguous
     196    // ranges of bits. The output range hsb..lsb will describe the second range of the value.
     197    // if the range is set, inverted will be false, and if the range is clear, inverted will
     198    // be true. For example (with width 8):
     199    //   00001111 = hsb:3, lsb:0, inverted:false
     200    //   11110000 = hsb:3, lsb:0, inverted:true
     201    //   00111100 = hsb:5, lsb:2, inverted:false
     202    //   11000011 = hsb:5, lsb:2, inverted:true
     203    template<unsigned width>
     204    static bool findBitRange(uint64_t value, unsigned& hsb, unsigned& lsb, bool& inverted)
     205    {
     206        ASSERT(value & mask(width - 1));
     207        ASSERT(value != mask(width - 1));
     208        ASSERT(!(value & ~mask(width - 1)));
     209
     210        // Detect cases where the top bit is set; if so, flip all the bits & set invert.
     211        // This halves the number of patterns we need to look for.
     212        const uint64_t msb = 1ull << (width - 1);
     213        if ((inverted = (value & msb)))
     214            value ^= mask(width - 1);
     215
     216        // Find the highest set bit in value, generate a corresponding mask & flip all
     217        // bits under it.
     218        hsb = highestSetBit(value);
     219        value ^= mask(hsb);
     220        if (!value) {
     221            // If this cleared the value, then the range hsb..0 was all set.
     222            lsb = 0;
     223            return true;
     224        }
     225
     226        // Try making one more mask, and flipping the bits!
     227        lsb = highestSetBit(value);
     228        value ^= mask(lsb);
     229        if (!value) {
     230            // Success - but lsb actually points to the hsb of a third range - add one
     231            // to get to the lsb of the mid range.
     232            ++lsb;
     233            return true;
     234        }
     235
     236        return false;
     237    }
     238
     239    // Encodes the set of immN:immr:imms fields found in a logical immediate.
     240    template<unsigned width>
     241    static int encodeLogicalImmediate(unsigned hsb, unsigned lsb, bool inverted)
     242    {
     243        // Check width is a power of 2!
     244        ASSERT(!(width & (width -1)));
     245        ASSERT(width <= 64 && width >= 2);
     246        ASSERT(hsb >= lsb);
     247        ASSERT(hsb < width);
     248
     249        int immN = 0;
     250        int imms = 0;
     251        int immr = 0;
     252
     253        // For 64-bit values this is easy - just set immN to true, and imms just
     254        // contains the bit number of the highest set bit of the set range. For
     255        // values with narrower widths, these are encoded by a leading set of
     256        // one bits, followed by a zero bit, followed by the remaining set of bits
     257        // being the high bit of the range. For a 32-bit immediate there are no
     258        // leading one bits, just a zero followed by a five bit number. For a
     259        // 16-bit immediate there is one one bit, a zero bit, and then a four bit
     260        // bit-position, etc.
     261        if (width == 64)
     262            immN = 1;
     263        else
     264            imms = 63 & ~(width + width - 1);
     265
     266        if (inverted) {
     267            // if width is 64 & hsb is 62, then we have a value something like:
     268            //   0x80000000ffffffff (in this case with lsb 32).
     269            // The ror should be by 1, imms (effectively set width minus 1) is
     270            // 32. Set width is full width minus cleared width.
     271            immr = (width - 1) - hsb;
     272            imms |= (width - ((hsb - lsb) + 1)) - 1;
     273        } else {
     274            // if width is 64 & hsb is 62, then we have a value something like:
     275            //   0x7fffffff00000000 (in this case with lsb 32).
     276            // The value is effectively rol'ed by lsb, which is equivalent to
     277            // a ror by width - lsb (or 0, in the case where lsb is 0). imms
     278            // is hsb - lsb.
     279            immr = (width - lsb) & (width - 1);
     280            imms |= hsb - lsb;
     281        }
     282
     283        return immN << 12 | immr << 6 | imms;
     284    }
     285
     286    static const int InvalidLogicalImmediate = -1;
     287
     288    int m_value;
     289};
     290
     291
    69292} // namespace JSC.
    70293
  • trunk/Source/JavaScriptCore/assembler/MacroAssemblerARM64.h

    r196544 r196736  
    368368    }
    369369
     370    void and64(TrustedImm64 imm, RegisterID src, RegisterID dest)
     371    {
     372        LogicalImmediate logicalImm = LogicalImmediate::create64(imm.m_value);
     373
     374        if (logicalImm.isValid()) {
     375            m_assembler.and_<64>(dest, src, logicalImm);
     376            return;
     377        }
     378
     379        move(imm, getCachedDataTempRegisterIDAndInvalidate());
     380        m_assembler.and_<64>(dest, src, dataTempRegister);
     381    }
     382
    370383    void and64(RegisterID src, RegisterID dest)
    371384    {
     
    579592        m_assembler.orr<64>(dest, src, dataTempRegister);
    580593    }
    581    
     594
     595    void or64(TrustedImm64 imm, RegisterID src, RegisterID dest)
     596    {
     597        LogicalImmediate logicalImm = LogicalImmediate::create64(imm.m_value);
     598
     599        if (logicalImm.isValid()) {
     600            m_assembler.orr<64>(dest, src, logicalImm);
     601            return;
     602        }
     603
     604        move(imm, getCachedDataTempRegisterIDAndInvalidate());
     605        m_assembler.orr<64>(dest, src, dataTempRegister);
     606    }
     607
    582608    void or64(TrustedImm64 imm, RegisterID dest)
    583609    {
     
    830856    {
    831857        xor64(imm, dest, dest);
     858    }
     859
     860    void xor64(TrustedImm64 imm, RegisterID src, RegisterID dest)
     861    {
     862        if (imm.m_value == -1)
     863            m_assembler.mvn<64>(dest, src);
     864        else {
     865            LogicalImmediate logicalImm = LogicalImmediate::create64(imm.m_value);
     866
     867            if (logicalImm.isValid()) {
     868                m_assembler.eor<64>(dest, src, logicalImm);
     869                return;
     870            }
     871
     872            move(imm, getCachedDataTempRegisterIDAndInvalidate());
     873            m_assembler.eor<64>(dest, src, dataTempRegister);
     874        }
    832875    }
    833876
  • trunk/Source/JavaScriptCore/b3/B3LowerToAir.cpp

    r196616 r196736  
    499499    }
    500500
     501    Arg bitImm(Value* value)
     502    {
     503        if (value->hasInt()) {
     504            int64_t intValue = value->asInt();
     505            if (Arg::isValidBitImmForm(intValue))
     506                return Arg::bitImm(intValue);
     507        }
     508        return Arg();
     509    }
     510
     511    Arg bitImm64(Value* value)
     512    {
     513        if (value->hasInt()) {
     514            int64_t intValue = value->asInt();
     515            if (Arg::isValidBitImm64Form(intValue))
     516                return Arg::bitImm64(intValue);
     517        }
     518        return Arg();
     519    }
     520
    501521    Arg immOrTmp(Value* value)
    502522    {
     
    643663                if (imm(left)) {
    644664                    append(opcode, imm(left), tmp(right), result);
     665                    return;
     666                }
     667            }
     668        }
     669
     670        if (isValidForm(opcode, Arg::BitImm, Arg::Tmp, Arg::Tmp)) {
     671            if (commutativity == Commutative) {
     672                if (Arg rightArg = bitImm(right)) {
     673                    append(opcode, rightArg, tmp(left), result);
     674                    return;
     675                }
     676            } else {
     677                // A non-commutative operation could have an immediate in left.
     678                if (Arg leftArg = bitImm(left)) {
     679                    append(opcode, leftArg, tmp(right), result);
     680                    return;
     681                }
     682            }
     683        }
     684
     685        if (isValidForm(opcode, Arg::BitImm64, Arg::Tmp, Arg::Tmp)) {
     686            if (commutativity == Commutative) {
     687                if (Arg rightArg = bitImm64(right)) {
     688                    append(opcode, rightArg, tmp(left), result);
     689                    return;
     690                }
     691            } else {
     692                // A non-commutative operation could have an immediate in left.
     693                if (Arg leftArg = bitImm64(left)) {
     694                    append(opcode, leftArg, tmp(right), result);
    645695                    return;
    646696                }
     
    929979                    arg = imm(value.value());
    930980                else if (value.value()->hasInt64())
    931                     arg = Arg::imm64(value.value()->asInt64());
     981                    arg = Arg::bigImm(value.value()->asInt64());
    932982                else if (value.value()->hasDouble() && canBeInternal(value.value())) {
    933983                    commitInternal(value.value());
    934                     arg = Arg::imm64(bitwise_cast<int64_t>(value.value()->asDouble()));
     984                    arg = Arg::bigImm(bitwise_cast<int64_t>(value.value()->asDouble()));
    935985                } else
    936986                    arg = tmp(value.value());
     
    19351985                append(Move, imm(m_value), tmp(m_value));
    19361986            else
    1937                 append(Move, Arg::imm64(m_value->asInt()), tmp(m_value));
     1987                append(Move, Arg::bigImm(m_value->asInt()), tmp(m_value));
    19381988            return;
    19391989        }
  • trunk/Source/JavaScriptCore/b3/B3StackmapSpecial.cpp

    r196616 r196736  
    208208    case Arg::Tmp:
    209209    case Arg::Imm:
    210     case Arg::Imm64:
     210    case Arg::BigImm:
    211211        break;
    212212    default:
     
    256256        break;
    257257    case Arg::Imm:
    258     case Arg::Imm64:
     258    case Arg::BigImm:
    259259        return ValueRep::constant(arg.value());
    260260        break;
  • trunk/Source/JavaScriptCore/b3/air/AirArg.cpp

    r195139 r196736  
    122122        out.print("$", m_offset);
    123123        return;
    124     case Imm64:
     124    case BigImm:
     125        out.printf("$0x%llx", static_cast<long long unsigned>(m_offset));
     126        return;
     127    case BitImm:
     128        out.print("$", m_offset);
     129        return;
     130    case BitImm64:
    125131        out.printf("$0x%llx", static_cast<long long unsigned>(m_offset));
    126132        return;
     
    186192        out.print("Imm");
    187193        return;
    188     case Arg::Imm64:
    189         out.print("Imm64");
     194    case Arg::BigImm:
     195        out.print("BigImm");
     196        return;
     197    case Arg::BitImm:
     198        out.print("BitImm");
     199        return;
     200    case Arg::BitImm64:
     201        out.print("BitImm64");
    190202        return;
    191203    case Arg::Addr:
  • trunk/Source/JavaScriptCore/b3/air/AirArg.h

    r195640 r196736  
    6161
    6262        // This is an immediate that the instruction will materialize. Imm is the immediate that can be
    63         // inlined into most instructions, while Imm64 indicates a constant materialization and is
     63        // inlined into most instructions, while BigImm indicates a constant materialization and is
    6464        // usually only usable with Move. Specials may also admit it, for example for stackmaps used for
    6565        // OSR exit and tail calls.
     66        // BitImm is an immediate for Bitwise operation (And, Xor, etc).
    6667        Imm,
    67         Imm64,
     68        BigImm,
     69        BitImm,
     70        BitImm64,
    6871
    6972        // These are the addresses. Instructions may load from (Use), store to (Def), or evaluate
     
    476479    }
    477480
    478     static Arg imm64(int64_t value)
     481    static Arg bigImm(int64_t value)
    479482    {
    480483        Arg result;
    481         result.m_kind = Imm64;
     484        result.m_kind = BigImm;
    482485        result.m_offset = value;
    483486        return result;
    484487    }
    485488
     489    static Arg bitImm(int64_t value)
     490    {
     491        Arg result;
     492        result.m_kind = BitImm;
     493        result.m_offset = value;
     494        return result;
     495    }
     496
     497    static Arg bitImm64(int64_t value)
     498    {
     499        Arg result;
     500        result.m_kind = BitImm64;
     501        result.m_offset = value;
     502        return result;
     503    }
     504
    486505    static Arg immPtr(const void* address)
    487506    {
    488         return imm64(bitwise_cast<intptr_t>(address));
     507        return bigImm(bitwise_cast<intptr_t>(address));
    489508    }
    490509
     
    653672    }
    654673
    655     bool isImm64() const
    656     {
    657         return kind() == Imm64;
     674    bool isBigImm() const
     675    {
     676        return kind() == BigImm;
     677    }
     678
     679    bool isBitImm() const
     680    {
     681        return kind() == BitImm;
     682    }
     683
     684    bool isBitImm64() const
     685    {
     686        return kind() == BitImm64;
    658687    }
    659688
    660689    bool isSomeImm() const
    661690    {
    662         return isImm() || isImm64();
     691        return isImm() || isBigImm() || isBitImm() || isBitImm64();
    663692    }
    664693
     
    748777    int64_t value() const
    749778    {
    750         ASSERT(kind() == Imm || kind() == Imm64);
     779        ASSERT(isSomeImm());
    751780        return m_offset;
    752781    }
     
    768797    void* pointerValue() const
    769798    {
    770         ASSERT(kind() == Imm64);
     799        ASSERT(kind() == BigImm);
    771800        return bitwise_cast<void*>(static_cast<intptr_t>(m_offset));
    772801    }
     
    838867        switch (kind()) {
    839868        case Imm:
    840         case Imm64:
     869        case BigImm:
     870        case BitImm:
     871        case BitImm64:
    841872        case Addr:
    842873        case Index:
     
    862893        switch (kind()) {
    863894        case Imm:
     895        case BitImm:
     896        case BitImm64:
    864897        case RelCond:
    865898        case ResCond:
     
    873906        case Stack:
    874907        case CallArg:
    875         case Imm64: // Yes, we allow Imm64 as a double immediate. We use this for implementing stackmaps.
     908        case BigImm: // Yes, we allow BigImm as a double immediate. We use this for implementing stackmaps.
    876909            return true;
    877910        case Tmp:
     
    885918        switch (kind()) {
    886919        case Imm:
     920        case BitImm:
     921        case BitImm64:
    887922        case Special:
    888923        case Tmp:
     
    9951030    }
    9961031
     1032    static bool isValidBitImmForm(int64_t value)
     1033    {
     1034        if (isX86())
     1035            return B3::isRepresentableAs<int32_t>(value);
     1036        if (isARM64())
     1037            return ARM64LogicalImmediate::create32(value).isValid();
     1038        return false;
     1039    }
     1040
     1041    static bool isValidBitImm64Form(int64_t value)
     1042    {
     1043        if (isX86())
     1044            return B3::isRepresentableAs<int32_t>(value);
     1045        if (isARM64())
     1046            return ARM64LogicalImmediate::create64(value).isValid();
     1047        return false;
     1048    }
     1049
    9971050    static bool isValidAddrForm(int32_t offset, Optional<Width> width = Nullopt)
    9981051    {
     
    10431096        case Imm:
    10441097            return isValidImmForm(value());
    1045         case Imm64:
    1046             return true;
     1098        case BigImm:
     1099            return true;
     1100        case BitImm:
     1101            return isValidBitImmForm(value());
     1102        case BitImm64:
     1103            return isValidBitImm64Form(value());
    10471104        case Addr:
    10481105        case Stack:
     
    11201177    MacroAssembler::TrustedImm32 asTrustedImm32() const
    11211178    {
    1122         ASSERT(isImm());
     1179        ASSERT(isImm() || isBitImm());
    11231180        return MacroAssembler::TrustedImm32(static_cast<int32_t>(m_offset));
    11241181    }
     
    11271184    MacroAssembler::TrustedImm64 asTrustedImm64() const
    11281185    {
    1129         ASSERT(isImm64());
     1186        ASSERT(isBigImm() || isBitImm64());
    11301187        return MacroAssembler::TrustedImm64(value());
    11311188    }
     
    11351192    {
    11361193        if (is64Bit())
    1137             ASSERT(isImm64());
     1194            ASSERT(isBigImm());
    11381195        else
    11391196            ASSERT(isImm());
  • trunk/Source/JavaScriptCore/b3/air/AirCCallSpecial.cpp

    r195298 r196736  
    7777                break;
    7878            return false;
    79         case Arg::Imm64:
     79        case Arg::BigImm:
    8080            if (is64Bit())
    8181                break;
     
    126126    switch (inst.args[calleeArgOffset].kind()) {
    127127    case Arg::Imm:
    128     case Arg::Imm64:
     128    case Arg::BigImm:
    129129        jit.move(inst.args[calleeArgOffset].asTrustedImmPtr(), scratchRegister);
    130130        jit.call(scratchRegister);
  • trunk/Source/JavaScriptCore/b3/air/AirEmitShuffle.cpp

    r195298 r196736  
    311311                ASSERT(pair.src().isSomeImm());
    312312                ASSERT(move == Move32);
    313                 result.append(Inst(Move, origin, Arg::imm64(pair.src().value()), scratch));
     313                result.append(Inst(Move, origin, Arg::bigImm(pair.src().value()), scratch));
    314314            }
    315315            result.append(Inst(moveForWidth(pair.width()), origin, scratch, pair.dst()));
  • trunk/Source/JavaScriptCore/b3/air/AirFixObviousSpills.cpp

    r196032 r196736  
    238238                    arg = Arg::imm(alias->constant);
    239239                else
    240                     arg = Arg::imm64(alias->constant);
     240                    arg = Arg::bigImm(alias->constant);
    241241                didThings = true;
    242242                return;
  • trunk/Source/JavaScriptCore/b3/air/AirOpcode.opcodes

    r196544 r196736  
    4040# Tmp => temporary or register
    4141# Imm => 32-bit immediate int
    42 # Imm64 => TrustedImm64
     42# BigImm => TrustedImm64
    4343# Addr => address as temporary/register+offset
    4444# Index => BaseIndex address
     
    271271And32 U:G:32, U:G:32, ZD:G:32
    272272    Tmp, Tmp, Tmp
     273    arm64: BitImm, Tmp, Tmp
    273274    x86: Tmp, Addr, Tmp
    274275    x86: Addr, Tmp, Tmp
     
    28328464: And64 U:G:64, U:G:64, D:G:64
    284285    Tmp, Tmp, Tmp
     286    arm64: BitImm64, Tmp, Tmp
    285287
    286288x86_64: And64 U:G:64, UD:G:64
     
    362364Or32 U:G:32, U:G:32, ZD:G:32
    363365    Tmp, Tmp, Tmp
     366    arm64: BitImm, Tmp, Tmp
    364367    x86: Tmp, Addr, Tmp
    365368    x86: Addr, Tmp, Tmp
     
    37437764: Or64 U:G:64, U:G:64, D:G:64
    375378    Tmp, Tmp, Tmp
     379    arm64: BitImm64, Tmp, Tmp
    376380
    37738164: Or64 U:G:64, UD:G:64
     
    381385Xor32 U:G:32, U:G:32, ZD:G:32
    382386    Tmp, Tmp, Tmp
     387    arm64: BitImm, Tmp, Tmp
    383388    x86: Tmp, Addr, Tmp
    384389    x86: Addr, Tmp, Tmp
     
    39339864: Xor64 U:G:64, U:G:64, D:G:64
    394399    Tmp, Tmp, Tmp
     400    arm64: BitImm64, Tmp, Tmp
    395401
    39640264: Xor64 U:G:64, UD:G:64
     
    465471    Tmp, Tmp
    466472    Imm, Tmp as signExtend32ToPtr
    467     Imm64, Tmp
     473    BigImm, Tmp
    468474    Addr, Tmp as loadPtr # This means that "Move Addr, Tmp" is code-generated as "load" not "move".
    469475    Index, Tmp as loadPtr
  • trunk/Source/JavaScriptCore/b3/air/opcode_generator.rb

    r196032 r196736  
    191191
    192192def isKind(token)
    193     token =~ /\A((Tmp)|(Imm)|(Imm64)|(Addr)|(Index)|(RelCond)|(ResCond)|(DoubleCond))\Z/
     193    token =~ /\A((Tmp)|(Imm)|(BigImm)|(BitImm)|(BitImm64)|(Addr)|(Index)|(RelCond)|(ResCond)|(DoubleCond))\Z/
    194194end
    195195
     
    265265    def consumeKind
    266266        result = token.string
    267         parseError("Expected kind (Imm, Imm64, Tmp, Addr, Index, RelCond, ResCond, or DoubleCond)") unless isKind(result)
     267        parseError("Expected kind (Imm, BigImm, BitImm, BitImm64, Tmp, Addr, Index, RelCond, ResCond, or DoubleCond)") unless isKind(result)
    268268        advance
    269269        result
     
    427427                        kinds.each_with_index {
    428428                            | kind, index |
    429                             if kind.name == "Imm" or kind.name == "Imm64"
     429                            if kind.name == "Imm" or kind.name == "BigImm" or kind.name == "BitImm" or kind.name == "BitImm64"
    430430                                if signature[index].role != "U"
    431431                                    parseError("Form has an immediate for a non-use argument")
     
    531531    groups.each_pair {
    532532        | key, value |
    533         outp.puts "#if USE(JSVALUE64)" if key == "Imm64"
     533        outp.puts "#if USE(JSVALUE64)" if key == "BigImm" or key == "BitImm64"
    534534        Kind.argKinds(key).each {
    535535            | argKind |
     
    538538        matchForms(outp, speed, value, columnIndex + 1, columnGetter, filter, callback)
    539539        outp.puts "break;"
    540         outp.puts "#endif // USE(JSVALUE64)" if key == "Imm64"
     540        outp.puts "#endif // USE(JSVALUE64)" if key == "BigImm" or key == "BitImm64"
    541541    }
    542542    outp.puts "default:"
     
    799799                    outp.puts "if (!Arg::isValidImmForm(args[#{index}].value()))"
    800800                    outp.puts "OPGEN_RETURN(false);"
     801                when "BitImm"
     802                    outp.puts "if (!Arg::isValidBitImmForm(args[#{index}].value()))"
     803                    outp.puts "OPGEN_RETURN(false);"
     804                when "BitImm64"
     805                    outp.puts "if (!Arg::isValidBitImm64Form(args[#{index}].value()))"
     806                    outp.puts "OPGEN_RETURN(false);"
    801807                when "Addr"
    802808                    if arg.role == "UA"
     
    810816                    outp.puts "if (!Arg::isValidIndexForm(args[#{index}].scale(), args[#{index}].offset(), #{arg.widthCode}))"
    811817                    outp.puts "OPGEN_RETURN(false);"
    812                 when "Imm64"
     818                when "BigImm"
    813819                when "RelCond"
    814820                when "ResCond"
     
    10561062                        outp.print "args[#{index}].fpr()"
    10571063                    end
    1058                 when "Imm"
     1064                when "Imm", "BitImm"
    10591065                    outp.print "args[#{index}].asTrustedImm32()"
    1060                 when "Imm64"
     1066                when "BigImm", "BitImm64"
    10611067                    outp.print "args[#{index}].asTrustedImm64()"
    10621068                when "Addr"
  • trunk/Source/JavaScriptCore/b3/air/testair.cpp

    r196032 r196736  
    127127
    128128    T* ptr = (*map)[value];
    129     block->append(Move, nullptr, Arg::imm64(bitwise_cast<intptr_t>(ptr)), scratch);
     129    block->append(Move, nullptr, Arg::bigImm(bitwise_cast<intptr_t>(ptr)), scratch);
    130130    block->append(move, nullptr, Arg::addr(scratch), tmp);
    131131}
     
    158158    int32_t things[4];
    159159    Tmp base = code.newTmp(Arg::GP);
    160     root->append(Move, nullptr, Arg::imm64(bitwise_cast<intptr_t>(&things)), base);
     160    root->append(Move, nullptr, Arg::bigImm(bitwise_cast<intptr_t>(&things)), base);
    161161    root->append(Move32, nullptr, Tmp(GPRInfo::regT0), Arg::addr(base, 0 * sizeof(int32_t)));
    162162    root->append(Move32, nullptr, Tmp(GPRInfo::regT1), Arg::addr(base, 1 * sizeof(int32_t)));
     
    193193    int32_t things[5];
    194194    Tmp base = code.newTmp(Arg::GP);
    195     root->append(Move, nullptr, Arg::imm64(bitwise_cast<intptr_t>(&things)), base);
     195    root->append(Move, nullptr, Arg::bigImm(bitwise_cast<intptr_t>(&things)), base);
    196196    root->append(Move32, nullptr, Tmp(GPRInfo::regT0), Arg::addr(base, 0 * sizeof(int32_t)));
    197197    root->append(Move32, nullptr, Tmp(GPRInfo::regT1), Arg::addr(base, 1 * sizeof(int32_t)));
     
    239239    int32_t things[8];
    240240    Tmp base = code.newTmp(Arg::GP);
    241     root->append(Move, nullptr, Arg::imm64(bitwise_cast<intptr_t>(&things)), base);
     241    root->append(Move, nullptr, Arg::bigImm(bitwise_cast<intptr_t>(&things)), base);
    242242    root->append(Move32, nullptr, Tmp(GPRInfo::regT0), Arg::addr(base, 0 * sizeof(int32_t)));
    243243    root->append(Move32, nullptr, Tmp(GPRInfo::regT1), Arg::addr(base, 1 * sizeof(int32_t)));
     
    291291    int32_t things[8];
    292292    Tmp base = code.newTmp(Arg::GP);
    293     root->append(Move, nullptr, Arg::imm64(bitwise_cast<intptr_t>(&things)), base);
     293    root->append(Move, nullptr, Arg::bigImm(bitwise_cast<intptr_t>(&things)), base);
    294294    root->append(Move32, nullptr, Tmp(GPRInfo::regT0), Arg::addr(base, 0 * sizeof(int32_t)));
    295295    root->append(Move32, nullptr, Tmp(GPRInfo::regT1), Arg::addr(base, 1 * sizeof(int32_t)));
     
    335335    int32_t things[4];
    336336    Tmp base = code.newTmp(Arg::GP);
    337     root->append(Move, nullptr, Arg::imm64(bitwise_cast<intptr_t>(&things)), base);
     337    root->append(Move, nullptr, Arg::bigImm(bitwise_cast<intptr_t>(&things)), base);
    338338    root->append(Move32, nullptr, Tmp(GPRInfo::regT0), Arg::addr(base, 0 * sizeof(int32_t)));
    339339    root->append(Move32, nullptr, Tmp(GPRInfo::regT1), Arg::addr(base, 1 * sizeof(int32_t)));
     
    371371    int32_t things[4];
    372372    Tmp base = code.newTmp(Arg::GP);
    373     root->append(Move, nullptr, Arg::imm64(bitwise_cast<intptr_t>(&things)), base);
     373    root->append(Move, nullptr, Arg::bigImm(bitwise_cast<intptr_t>(&things)), base);
    374374    root->append(Move32, nullptr, Tmp(GPRInfo::regT0), Arg::addr(base, 0 * sizeof(int32_t)));
    375375    root->append(Move32, nullptr, Tmp(GPRInfo::regT1), Arg::addr(base, 1 * sizeof(int32_t)));
     
    415415    Vector<int32_t> things(regs.size(), 666);
    416416    Tmp base = code.newTmp(Arg::GP);
    417     root->append(Move, nullptr, Arg::imm64(bitwise_cast<intptr_t>(&things[0])), base);
     417    root->append(Move, nullptr, Arg::bigImm(bitwise_cast<intptr_t>(&things[0])), base);
    418418    for (unsigned i = 0; i < regs.size(); ++i) {
    419419        root->append(Move32, nullptr, Arg::stack(slot, i * sizeof(int32_t)), Tmp(GPRInfo::regT0));
     
    456456    int32_t things[8];
    457457    Tmp base = code.newTmp(Arg::GP);
    458     root->append(Move, nullptr, Arg::imm64(bitwise_cast<intptr_t>(&things)), base);
     458    root->append(Move, nullptr, Arg::bigImm(bitwise_cast<intptr_t>(&things)), base);
    459459    root->append(Move32, nullptr, Tmp(GPRInfo::regT0), Arg::addr(base, 0 * sizeof(int32_t)));
    460460    root->append(Move32, nullptr, Tmp(GPRInfo::regT1), Arg::addr(base, 1 * sizeof(int32_t)));
     
    508508    int32_t things[8];
    509509    Tmp base = code.newTmp(Arg::GP);
    510     root->append(Move, nullptr, Arg::imm64(bitwise_cast<intptr_t>(&things)), base);
     510    root->append(Move, nullptr, Arg::bigImm(bitwise_cast<intptr_t>(&things)), base);
    511511    root->append(Move32, nullptr, Tmp(GPRInfo::regT0), Arg::addr(base, 0 * sizeof(int32_t)));
    512512    root->append(Move32, nullptr, Tmp(GPRInfo::regT1), Arg::addr(base, 1 * sizeof(int32_t)));
     
    563563    int32_t things[8];
    564564    Tmp base = code.newTmp(Arg::GP);
    565     root->append(Move, nullptr, Arg::imm64(bitwise_cast<intptr_t>(&things)), base);
     565    root->append(Move, nullptr, Arg::bigImm(bitwise_cast<intptr_t>(&things)), base);
    566566    root->append(Move32, nullptr, Tmp(GPRInfo::regT0), Arg::addr(base, 0 * sizeof(int32_t)));
    567567    root->append(Move32, nullptr, Tmp(GPRInfo::regT1), Arg::addr(base, 1 * sizeof(int32_t)));
     
    610610    int32_t things[6];
    611611    Tmp base = code.newTmp(Arg::GP);
    612     root->append(Move, nullptr, Arg::imm64(bitwise_cast<intptr_t>(&things)), base);
     612    root->append(Move, nullptr, Arg::bigImm(bitwise_cast<intptr_t>(&things)), base);
    613613    root->append(Move32, nullptr, Tmp(GPRInfo::regT0), Arg::addr(base, 0 * sizeof(int32_t)));
    614614    root->append(Move32, nullptr, Tmp(GPRInfo::regT1), Arg::addr(base, 1 * sizeof(int32_t)));
     
    655655    int32_t things[6];
    656656    Tmp base = code.newTmp(Arg::GP);
    657     root->append(Move, nullptr, Arg::imm64(bitwise_cast<intptr_t>(&things)), base);
     657    root->append(Move, nullptr, Arg::bigImm(bitwise_cast<intptr_t>(&things)), base);
    658658    root->append(Move32, nullptr, Tmp(GPRInfo::regT0), Arg::addr(base, 0 * sizeof(int32_t)));
    659659    root->append(Move32, nullptr, Tmp(GPRInfo::regT1), Arg::addr(base, 1 * sizeof(int32_t)));
     
    700700    int32_t things[6];
    701701    Tmp base = code.newTmp(Arg::GP);
    702     root->append(Move, nullptr, Arg::imm64(bitwise_cast<intptr_t>(&things)), base);
     702    root->append(Move, nullptr, Arg::bigImm(bitwise_cast<intptr_t>(&things)), base);
    703703    root->append(Move32, nullptr, Tmp(GPRInfo::regT0), Arg::addr(base, 0 * sizeof(int32_t)));
    704704    root->append(Move32, nullptr, Tmp(GPRInfo::regT1), Arg::addr(base, 1 * sizeof(int32_t)));
     
    745745    int32_t things[6];
    746746    Tmp base = code.newTmp(Arg::GP);
    747     root->append(Move, nullptr, Arg::imm64(bitwise_cast<intptr_t>(&things)), base);
     747    root->append(Move, nullptr, Arg::bigImm(bitwise_cast<intptr_t>(&things)), base);
    748748    root->append(Move32, nullptr, Tmp(GPRInfo::regT0), Arg::addr(base, 0 * sizeof(int32_t)));
    749749    root->append(Move32, nullptr, Tmp(GPRInfo::regT1), Arg::addr(base, 1 * sizeof(int32_t)));
     
    790790    int32_t things[6];
    791791    Tmp base = code.newTmp(Arg::GP);
    792     root->append(Move, nullptr, Arg::imm64(bitwise_cast<intptr_t>(&things)), base);
     792    root->append(Move, nullptr, Arg::bigImm(bitwise_cast<intptr_t>(&things)), base);
    793793    root->append(Move32, nullptr, Tmp(GPRInfo::regT0), Arg::addr(base, 0 * sizeof(int32_t)));
    794794    root->append(Move32, nullptr, Tmp(GPRInfo::regT1), Arg::addr(base, 1 * sizeof(int32_t)));
     
    834834    int32_t things[6];
    835835    Tmp base = code.newTmp(Arg::GP);
    836     root->append(Move, nullptr, Arg::imm64(bitwise_cast<intptr_t>(&things)), base);
     836    root->append(Move, nullptr, Arg::bigImm(bitwise_cast<intptr_t>(&things)), base);
    837837    root->append(Move32, nullptr, Tmp(GPRInfo::regT0), Arg::addr(base, 0 * sizeof(int32_t)));
    838838    root->append(Move32, nullptr, Tmp(GPRInfo::regT1), Arg::addr(base, 1 * sizeof(int32_t)));
     
    876876    Vector<int32_t> things(regs.size(), 666);
    877877    Tmp base = code.newTmp(Arg::GP);
    878     root->append(Move, nullptr, Arg::imm64(bitwise_cast<intptr_t>(&things[0])), base);
     878    root->append(Move, nullptr, Arg::bigImm(bitwise_cast<intptr_t>(&things[0])), base);
    879879    for (unsigned i = 0; i < regs.size(); ++i) {
    880880        root->append(Move32, nullptr, Arg::stack(slot, i * sizeof(int32_t)), Tmp(GPRInfo::regT0));
     
    913913    Vector<int32_t> things(regs.size(), 666);
    914914    Tmp base = code.newTmp(Arg::GP);
    915     root->append(Move, nullptr, Arg::imm64(bitwise_cast<intptr_t>(&things[0])), base);
     915    root->append(Move, nullptr, Arg::bigImm(bitwise_cast<intptr_t>(&things[0])), base);
    916916    for (unsigned i = 0; i < regs.size(); ++i) {
    917917        root->append(Move32, nullptr, Arg::stack(slot, i * sizeof(int32_t)), Tmp(GPRInfo::regT0));
     
    946946    int64_t things[4];
    947947    Tmp base = code.newTmp(Arg::GP);
    948     root->append(Move, nullptr, Arg::imm64(bitwise_cast<intptr_t>(&things)), base);
     948    root->append(Move, nullptr, Arg::bigImm(bitwise_cast<intptr_t>(&things)), base);
    949949    root->append(Move, nullptr, Tmp(GPRInfo::regT0), Arg::addr(base, 0 * sizeof(int64_t)));
    950950    root->append(Move, nullptr, Tmp(GPRInfo::regT1), Arg::addr(base, 1 * sizeof(int64_t)));
     
    982982    int64_t things[5];
    983983    Tmp base = code.newTmp(Arg::GP);
    984     root->append(Move, nullptr, Arg::imm64(bitwise_cast<intptr_t>(&things)), base);
     984    root->append(Move, nullptr, Arg::bigImm(bitwise_cast<intptr_t>(&things)), base);
    985985    root->append(Move, nullptr, Tmp(GPRInfo::regT0), Arg::addr(base, 0 * sizeof(int64_t)));
    986986    root->append(Move, nullptr, Tmp(GPRInfo::regT1), Arg::addr(base, 1 * sizeof(int64_t)));
     
    10191019    int64_t things[4];
    10201020    Tmp base = code.newTmp(Arg::GP);
    1021     root->append(Move, nullptr, Arg::imm64(bitwise_cast<intptr_t>(&things)), base);
     1021    root->append(Move, nullptr, Arg::bigImm(bitwise_cast<intptr_t>(&things)), base);
    10221022    root->append(Move, nullptr, Tmp(GPRInfo::regT0), Arg::addr(base, 0 * sizeof(int64_t)));
    10231023    root->append(Move, nullptr, Tmp(GPRInfo::regT1), Arg::addr(base, 1 * sizeof(int64_t)));
     
    10551055    int64_t things[5];
    10561056    Tmp base = code.newTmp(Arg::GP);
    1057     root->append(Move, nullptr, Arg::imm64(bitwise_cast<intptr_t>(&things)), base);
     1057    root->append(Move, nullptr, Arg::bigImm(bitwise_cast<intptr_t>(&things)), base);
    10581058    root->append(Move, nullptr, Tmp(GPRInfo::regT0), Arg::addr(base, 0 * sizeof(int64_t)));
    10591059    root->append(Move, nullptr, Tmp(GPRInfo::regT1), Arg::addr(base, 1 * sizeof(int64_t)));
     
    10961096    int32_t things[2];
    10971097    Tmp base = code.newTmp(Arg::GP);
    1098     root->append(Move, nullptr, Arg::imm64(bitwise_cast<intptr_t>(&things)), base);
     1098    root->append(Move, nullptr, Arg::bigImm(bitwise_cast<intptr_t>(&things)), base);
    10991099    root->append(Move32, nullptr, Tmp(GPRInfo::regT0), Arg::addr(base, 0 * sizeof(int32_t)));
    11001100    root->append(Move32, nullptr, Tmp(GPRInfo::regT1), Arg::addr(base, 1 * sizeof(int32_t)));
     
    11421142    int32_t things[3];
    11431143    Tmp base = code.newTmp(Arg::GP);
    1144     root->append(Move, nullptr, Arg::imm64(bitwise_cast<intptr_t>(&things)), base);
     1144    root->append(Move, nullptr, Arg::bigImm(bitwise_cast<intptr_t>(&things)), base);
    11451145    root->append(Move32, nullptr, Tmp(GPRInfo::regT0), Arg::addr(base, 0 * sizeof(int32_t)));
    11461146    root->append(Move32, nullptr, Tmp(GPRInfo::regT1), Arg::addr(base, 1 * sizeof(int32_t)));
     
    11921192
    11931193    Vector<int32_t> things(regs.size(), 666);
    1194     root->append(Move, nullptr, Arg::imm64(bitwise_cast<intptr_t>(&things[0])), Tmp(GPRInfo::regT0));
     1194    root->append(Move, nullptr, Arg::bigImm(bitwise_cast<intptr_t>(&things[0])), Tmp(GPRInfo::regT0));
    11951195    for (unsigned i = 0; i < regs.size(); ++i) {
    11961196        root->append(
     
    12421242
    12431243    Vector<int64_t> things(regs.size(), 666);
    1244     root->append(Move, nullptr, Arg::imm64(bitwise_cast<intptr_t>(&things[0])), Tmp(GPRInfo::regT0));
     1244    root->append(Move, nullptr, Arg::bigImm(bitwise_cast<intptr_t>(&things[0])), Tmp(GPRInfo::regT0));
    12451245    for (unsigned i = 0; i < regs.size(); ++i) {
    12461246        root->append(
     
    13061306
    13071307    Vector<int64_t> things(regs.size(), 666);
    1308     root->append(Move, nullptr, Arg::imm64(bitwise_cast<intptr_t>(&things[0])), Tmp(GPRInfo::regT0));
     1308    root->append(Move, nullptr, Arg::bigImm(bitwise_cast<intptr_t>(&things[0])), Tmp(GPRInfo::regT0));
    13091309    for (unsigned i = 0; i < regs.size(); ++i) {
    13101310        root->append(
     
    13551355    int32_t things[2];
    13561356    Tmp base = code.newTmp(Arg::GP);
    1357     root->append(Move, nullptr, Arg::imm64(bitwise_cast<intptr_t>(&things)), base);
     1357    root->append(Move, nullptr, Arg::bigImm(bitwise_cast<intptr_t>(&things)), base);
    13581358    root->append(Move32, nullptr, Tmp(GPRInfo::regT0), Arg::addr(base, 0 * sizeof(int32_t)));
    13591359    root->append(Move32, nullptr, Tmp(GPRInfo::regT1), Arg::addr(base, 1 * sizeof(int32_t)));
     
    14001400    int64_t things[2];
    14011401    Tmp base = code.newTmp(Arg::GP);
    1402     root->append(Move, nullptr, Arg::imm64(bitwise_cast<intptr_t>(&things)), base);
     1402    root->append(Move, nullptr, Arg::bigImm(bitwise_cast<intptr_t>(&things)), base);
    14031403    root->append(Move, nullptr, Tmp(GPRInfo::regT0), Arg::addr(base, 0 * sizeof(int64_t)));
    14041404    root->append(Move, nullptr, Tmp(GPRInfo::regT1), Arg::addr(base, 1 * sizeof(int64_t)));
     
    14451445    int64_t things[2];
    14461446    Tmp base = code.newTmp(Arg::GP);
    1447     root->append(Move, nullptr, Arg::imm64(bitwise_cast<intptr_t>(&things)), base);
     1447    root->append(Move, nullptr, Arg::bigImm(bitwise_cast<intptr_t>(&things)), base);
    14481448    root->append(Move, nullptr, Tmp(GPRInfo::regT0), Arg::addr(base, 0 * sizeof(int64_t)));
    14491449    root->append(Move, nullptr, Tmp(GPRInfo::regT1), Arg::addr(base, 1 * sizeof(int64_t)));
     
    14951495
    14961496    Vector<int64_t> things(regs.size(), 666);
    1497     root->append(Move, nullptr, Arg::imm64(bitwise_cast<intptr_t>(&things[0])), Tmp(GPRInfo::regT0));
     1497    root->append(Move, nullptr, Arg::bigImm(bitwise_cast<intptr_t>(&things[0])), Tmp(GPRInfo::regT0));
    14981498    for (unsigned i = 0; i < regs.size(); ++i) {
    14991499        root->append(
     
    15471547
    15481548    Vector<int64_t> things(regs.size(), 666);
    1549     root->append(Move, nullptr, Arg::imm64(bitwise_cast<intptr_t>(&things[0])), Tmp(GPRInfo::regT0));
     1549    root->append(Move, nullptr, Arg::bigImm(bitwise_cast<intptr_t>(&things[0])), Tmp(GPRInfo::regT0));
    15501550    for (unsigned i = 0; i < regs.size(); ++i) {
    15511551        root->append(
     
    15821582    double things[4];
    15831583    Tmp base = code.newTmp(Arg::GP);
    1584     root->append(Move, nullptr, Arg::imm64(bitwise_cast<intptr_t>(&things)), base);
     1584    root->append(Move, nullptr, Arg::bigImm(bitwise_cast<intptr_t>(&things)), base);
    15851585    root->append(MoveDouble, nullptr, Tmp(FPRInfo::fpRegT0), Arg::addr(base, 0 * sizeof(double)));
    15861586    root->append(MoveDouble, nullptr, Tmp(FPRInfo::fpRegT1), Arg::addr(base, 1 * sizeof(double)));
     
    16161616    double things[4];
    16171617    Tmp base = code.newTmp(Arg::GP);
    1618     root->append(Move, nullptr, Arg::imm64(bitwise_cast<intptr_t>(&things)), base);
     1618    root->append(Move, nullptr, Arg::bigImm(bitwise_cast<intptr_t>(&things)), base);
    16191619    root->append(MoveDouble, nullptr, Tmp(FPRInfo::fpRegT0), Arg::addr(base, 0 * sizeof(double)));
    16201620    root->append(MoveDouble, nullptr, Tmp(FPRInfo::fpRegT1), Arg::addr(base, 1 * sizeof(double)));
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