Changeset 205656 in webkit

Timestamp:

Sep 8, 2016 1:05:28 PM (8 years ago)

Author:

mark.lam@apple.com

Message:

Add support for a ternary sub32 emitter for ARM64 and 32-bit ARM.
​https://bugs.webkit.org/show_bug.cgi?id=161724

Reviewed by Filip Pizlo.

ARM architectures support ternary sub instructions. We should make use of them
in emitAllocateWithNonNullAllocator().

• assembler/MacroAssemblerARM.h:

(JSC::MacroAssemblerARM::sub32):

• assembler/MacroAssemblerARM64.h:

(JSC::MacroAssemblerARM64::sub32):

• assembler/MacroAssemblerARMv7.h:

(JSC::MacroAssemblerARMv7::sub32):

• assembler/MacroAssemblerSH4.h:

(JSC::MacroAssemblerSH4::sub32):

• assembler/MacroAssemblerX86Common.h:

(JSC::MacroAssemblerX86Common::sub32):

• b3/air/AirOpcode.opcodes:
• b3/testb3.cpp:

(JSC::B3::testTernarySubInstructionSelection):
(JSC::B3::run):

• jit/AssemblyHelpers.h:

(JSC::AssemblyHelpers::emitAllocateWithNonNullAllocator):

Location:

trunk/Source/JavaScriptCore

Files:

• ChangeLog (modified) (1 diff)
• assembler/MacroAssemblerARM.h (modified) (2 diffs)
• assembler/MacroAssemblerARM64.h (modified) (2 diffs)
• assembler/MacroAssemblerARMv7.h (modified) (2 diffs)
• assembler/MacroAssemblerSH4.h (modified) (2 diffs)
• assembler/MacroAssemblerX86Common.h (modified) (1 diff)
• b3/air/AirOpcode.opcodes (modified) (2 diffs)
• b3/testb3.cpp (modified) (2 diffs)
• jit/AssemblyHelpers.h (modified) (1 diff)

trunk/Source/JavaScriptCore/ChangeLog

@@ +1 @@
+2016-09-08  Mark Lam  <mark.lam@apple.com>
+
+        Add support for a ternary sub32 emitter for ARM64 and 32-bit ARM.
+        https://bugs.webkit.org/show_bug.cgi?id=161724
+
+        Reviewed by Filip Pizlo.
+
+        ARM architectures support ternary sub instructions.  We should make use of them
+        in emitAllocateWithNonNullAllocator().
+
+        * assembler/MacroAssemblerARM.h:
+        (JSC::MacroAssemblerARM::sub32):
+        * assembler/MacroAssemblerARM64.h:
+        (JSC::MacroAssemblerARM64::sub32):
+        * assembler/MacroAssemblerARMv7.h:
+        (JSC::MacroAssemblerARMv7::sub32):
+        * assembler/MacroAssemblerSH4.h:
+        (JSC::MacroAssemblerSH4::sub32):
+        * assembler/MacroAssemblerX86Common.h:
+        (JSC::MacroAssemblerX86Common::sub32):
+        * b3/air/AirOpcode.opcodes:
+        * b3/testb3.cpp:
+        (JSC::B3::testTernarySubInstructionSelection):
+        (JSC::B3::run):
+        * jit/AssemblyHelpers.h:
+        (JSC::AssemblyHelpers::emitAllocateWithNonNullAllocator):
+
 2016-09-08  Filip Pizlo  <fpizlo@apple.com>
 

trunk/Source/JavaScriptCore/assembler/MacroAssemblerARM.h

@@ -1 +1 @@
 /*
- * Copyright (C) 2008, 2013-2015 Apple Inc.
+ * Copyright (C) 2008, 2013-2016 Apple Inc.
  * Copyright (C) 2009, 2010 University of Szeged
  * All rights reserved.
@@ -315 +315 @@
     }
 
+    void sub32(RegisterID left, RegisterID right, RegisterID dest)
+    {
+        m_assembler.subs(dest, left, right);
+    }
+
     void sub32(TrustedImm32 imm, RegisterID dest)
     {

trunk/Source/JavaScriptCore/assembler/MacroAssemblerARM64.h

@@ -1 +1 @@
 /*
- * Copyright (C) 2012, 2014, 2015 Apple Inc. All rights reserved.
+ * Copyright (C) 2012, 2014-2016 Apple Inc. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -706 +706 @@
     }
 
+    void sub32(RegisterID left, RegisterID right, RegisterID dest)
+    {
+        m_assembler.sub<32>(dest, left, right);
+    }
+
     void sub32(TrustedImm32 imm, RegisterID dest)
     {

trunk/Source/JavaScriptCore/assembler/MacroAssemblerARMv7.h

@@ -1 +1 @@
 /*
- * Copyright (C) 2009-2010, 2014-2015 Apple Inc. All rights reserved.
+ * Copyright (C) 2009-2010, 2014-2016 Apple Inc. All rights reserved.
  * Copyright (C) 2010 University of Szeged
  *
@@ -463 +463 @@
     }
 
+    void sub32(RegisterID left, RegisterID right, RegisterID dest)
+    {
+        m_assembler.sub(dest, left, right);
+    }
+
     void sub32(TrustedImm32 imm, RegisterID dest)
     {

trunk/Source/JavaScriptCore/assembler/MacroAssemblerSH4.h

@@ -2 +2 @@
  * Copyright (C) 2013 Cisco Systems, Inc. All rights reserved.
  * Copyright (C) 2009-2011 STMicroelectronics. All rights reserved.
- * Copyright (C) 2008, 2014 Apple Inc. All rights reserved.
+ * Copyright (C) 2008, 2014, 2016 Apple Inc. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -420 +420 @@
     }
 
+    void sub32(RegisterID left, RegisterID right, RegisterID dest)
+    {
+        if (dest == right) {
+            neg32(dest);
+            add32(left, dest);
+            return;
+        }
+        move(left, dest);
+        sub32(right, dest);
+    }
+
     void sub32(TrustedImm32 imm, AbsoluteAddress address)
     {

trunk/Source/JavaScriptCore/assembler/MacroAssemblerX86Common.h

@@ -561 +561 @@
         m_assembler.subl_rr(src, dest);
     }
-    
+
+    void sub32(RegisterID left, RegisterID right, RegisterID dest)
+    {
+        if (dest == right) {
+            neg32(dest);
+            add32(left, dest);
+            return;
+        }
+        move(left, dest);
+        sub32(right, dest);
+    }
+
     void sub32(TrustedImm32 imm, RegisterID dest)
     {

trunk/Source/JavaScriptCore/b3/air/AirOpcode.opcodes

@@ -171 +171 @@
     x86: Tmp, Addr
 
+arm64: Sub32 U:G:32, U:G:32, D:G:32
+    Tmp, Tmp, Tmp
+
 64: Sub64 U:G:64, UD:G:64
     Tmp, Tmp
@@ -177 +180 @@
     x86: Addr, Tmp
     x86: Tmp, Addr
+
+arm64: Sub64 U:G:64, U:G:64, D:G:64
+    Tmp, Tmp, Tmp
 
 SubDouble U:F:64, U:F:64, D:F:64

trunk/Source/JavaScriptCore/b3/testb3.cpp

@@ -2169 +2169 @@
     CHECK(isIdentical(compileAndRun<int32_t>(proc, bitwise_cast<int32_t>(a), bitwise_cast<int32_t>(b), &effect), bitwise_cast<int32_t>(a - b)));
     CHECK(isIdentical(effect, static_cast<double>(a) - static_cast<double>(b)));
+}
+
+void testTernarySubInstructionSelection(B3::Opcode valueModifier, Type valueType, Air::Opcode expectedOpcode)
+{
+    Procedure proc;
+    BasicBlock* root = proc.addBlock();
+
+    Value* left = root->appendNew<ArgumentRegValue>(proc, Origin(), GPRInfo::argumentGPR0);
+    Value* right = root->appendNew<ArgumentRegValue>(proc, Origin(), GPRInfo::argumentGPR1);
+
+    if (valueModifier == Trunc) {
+        left = root->appendNew<Value>(proc, valueModifier, valueType, Origin(), left);
+        right = root->appendNew<Value>(proc, valueModifier, valueType, Origin(), right);
+    }
+
+    root->appendNewControlValue(
+        proc, Return, Origin(),
+        root->appendNew<Value>(proc, Sub, Origin(), left, right));
+
+    lowerToAirForTesting(proc);
+
+    auto block = proc.code()[0];
+    unsigned numberOfSubInstructions = 0;
+    for (auto instruction : *block) {
+        if (instruction.opcode == expectedOpcode) {
+            CHECK_EQ(instruction.args.size(), 3ul);
+            CHECK_EQ(instruction.args[0].kind(), Air::Arg::Tmp);
+            CHECK_EQ(instruction.args[1].kind(), Air::Arg::Tmp);
+            CHECK_EQ(instruction.args[2].kind(), Air::Arg::Tmp);
+            numberOfSubInstructions++;
+        }
+    }
+    CHECK_EQ(numberOfSubInstructions, 1ul);
 }
 
@@ -14426 +14459 @@
     }
 
+    if (isARM64()) {
+        RUN(testTernarySubInstructionSelection(Identity, Int64, Air::Sub64));
+        RUN(testTernarySubInstructionSelection(Trunc, Int32, Air::Sub32));
+    }
+
     if (tasks.isEmpty())
         usage();

trunk/Source/JavaScriptCore/jit/AssemblyHelpers.h

@@ -1432 +1432 @@
                 sub32(Address(allocatorGPR, MarkedAllocator::offsetOfCellSize()), scratchGPR);
             } else {
-                // FIXME: We need a 3-operand sub, and ARM totally has it!
                 load32(Address(allocatorGPR, MarkedAllocator::offsetOfCellSize()), scratchGPR);
-                neg32(scratchGPR);
-                add32(resultGPR, scratchGPR);
+                sub32(resultGPR, scratchGPR, scratchGPR);
             }
         }