Changeset 224258 in webkit
- Timestamp:
- Oct 31, 2017 4:12:32 PM (6 years ago)
- Location:
- trunk/Source/JavaScriptCore
- Files:
-
- 13 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/Source/JavaScriptCore/ChangeLog
r224254 r224258 1 2017-10-31 Commit Queue <commit-queue@webkit.org> 2 3 Unreviewed, rolling out r224243, r224246, and r224248. 4 https://bugs.webkit.org/show_bug.cgi?id=179083 5 6 The patch and fix broke the Windows build. (Requested by 7 mlewis13 on #webkit). 8 9 Reverted changesets: 10 11 "StructureStubInfo should have GPRReg members not int8_ts" 12 https://bugs.webkit.org/show_bug.cgi?id=179071 13 https://trac.webkit.org/changeset/224243 14 15 "Make all register enums be backed by uint8_t." 16 https://bugs.webkit.org/show_bug.cgi?id=179074 17 https://trac.webkit.org/changeset/224246 18 19 "Unreviewed, windows build fix." 20 https://trac.webkit.org/changeset/224248 21 1 22 2017-10-31 Tim Horton <timothy_horton@apple.com> 2 23 -
trunk/Source/JavaScriptCore/assembler/ARM64Assembler.h
r224246 r224258 158 158 namespace ARM64Registers { 159 159 160 enum RegisterID : uint8_t{160 typedef enum { 161 161 // Parameter/result registers. 162 162 x0, … … 204 204 x30 = lr, 205 205 zr = 0x3f, 206 } ;207 208 enum SPRegisterID : uint8_t{206 } RegisterID; 207 208 typedef enum { 209 209 pc, 210 210 nzcv, 211 211 fpsr 212 } ;212 } SPRegisterID; 213 213 214 214 // ARM64 always has 32 FPU registers 128-bits each. See http://llvm.org/devmtg/2012-11/Northover-AArch64.pdf 215 215 // and Section 5.1.2 in http://infocenter.arm.com/help/topic/com.arm.doc.ihi0055b/IHI0055B_aapcs64.pdf. 216 216 // However, we only use them for 64-bit doubles. 217 enum FPRegisterID : uint8_t{217 typedef enum { 218 218 // Parameter/result registers. 219 219 q0, … … 251 251 q30, 252 252 q31, 253 } ;253 } FPRegisterID; 254 254 255 255 static constexpr bool isSp(RegisterID reg) { return reg == sp; } -
trunk/Source/JavaScriptCore/assembler/ARMAssembler.h
r224246 r224258 39 39 namespace ARMRegisters { 40 40 41 enum RegisterID : uint8_t{41 typedef enum { 42 42 r0, 43 43 r1, … … 64 64 r14 = lr, 65 65 r15 = pc 66 } ;67 68 enum SPRegisterID : uint8_t{66 } RegisterID; 67 68 typedef enum { 69 69 apsr, 70 70 fpscr 71 } ;72 73 enum FPRegisterID : uint8_t{71 } SPRegisterID; 72 73 typedef enum { 74 74 d0, 75 75 d1, … … 109 109 // Pseudonyms for some of the registers. 110 110 SD0 = d7, /* Same as thumb assembler. */ 111 } ;111 } FPRegisterID; 112 112 113 113 } // namespace ARMRegisters -
trunk/Source/JavaScriptCore/assembler/ARMv7Assembler.h
r224246 r224258 40 40 namespace ARMRegisters { 41 41 42 enum RegisterID : uint8_t{43 r0,44 r1,45 r2,46 r3,47 r4,48 r5,49 r6,50 r7,51 r8,52 r9,53 r10,54 r11,55 r12,56 r13,57 r14,58 r15,59 60 fp = r7, // frame pointer61 sb = r9, // static base62 sl = r10, // stack limit63 ip = r12,64 sp = r13,65 lr = r14,66 pc = r1567 };68 69 enum SPRegisterID : uint8_t{70 apsr,71 fpscr72 };73 74 enum FPSingleRegisterID : uint8_t{75 s0,76 s1,77 s2,78 s3,79 s4,80 s5,81 s6,82 s7,83 s8,84 s9,85 s10,86 s11,87 s12,88 s13,89 s14,90 s15,91 s16,92 s17,93 s18,94 s19,95 s20,96 s21,97 s22,98 s23,99 s24,100 s25,101 s26,102 s27,103 s28,104 s29,105 s30,106 s31,107 };108 109 enum FPDoubleRegisterID : uint8_t{110 d0,111 d1,112 d2,113 d3,114 d4,115 d5,116 d6,117 d7,118 d8,119 d9,120 d10,121 d11,122 d12,123 d13,124 d14,125 d15,42 typedef enum { 43 r0, 44 r1, 45 r2, 46 r3, 47 r4, 48 r5, 49 r6, 50 r7, 51 r8, 52 r9, 53 r10, 54 r11, 55 r12, 56 r13, 57 r14, 58 r15, 59 60 fp = r7, // frame pointer 61 sb = r9, // static base 62 sl = r10, // stack limit 63 ip = r12, 64 sp = r13, 65 lr = r14, 66 pc = r15 67 } RegisterID; 68 69 typedef enum { 70 apsr, 71 fpscr 72 } SPRegisterID; 73 74 typedef enum { 75 s0, 76 s1, 77 s2, 78 s3, 79 s4, 80 s5, 81 s6, 82 s7, 83 s8, 84 s9, 85 s10, 86 s11, 87 s12, 88 s13, 89 s14, 90 s15, 91 s16, 92 s17, 93 s18, 94 s19, 95 s20, 96 s21, 97 s22, 98 s23, 99 s24, 100 s25, 101 s26, 102 s27, 103 s28, 104 s29, 105 s30, 106 s31, 107 } FPSingleRegisterID; 108 109 typedef enum { 110 d0, 111 d1, 112 d2, 113 d3, 114 d4, 115 d5, 116 d6, 117 d7, 118 d8, 119 d9, 120 d10, 121 d11, 122 d12, 123 d13, 124 d14, 125 d15, 126 126 #if CPU(ARM_NEON) || CPU(ARM_VFP_V3_D32) 127 d16,128 d17,129 d18,130 d19,131 d20,132 d21,133 d22,134 d23,135 d24,136 d25,137 d26,138 d27,139 d28,140 d29,141 d30,142 d31,127 d16, 128 d17, 129 d18, 130 d19, 131 d20, 132 d21, 133 d22, 134 d23, 135 d24, 136 d25, 137 d26, 138 d27, 139 d28, 140 d29, 141 d30, 142 d31, 143 143 #endif // CPU(ARM_NEON) || CPU(ARM_VFP_V3_D32) 144 };144 } FPDoubleRegisterID; 145 145 146 146 #if CPU(ARM_NEON) 147 enum FPQuadRegisterID : uint8_t{148 q0,149 q1,150 q2,151 q3,152 q4,153 q5,154 q6,155 q7,156 q8,157 q9,158 q10,159 q11,160 q12,161 q13,162 q14,163 q15,164 };147 typedef enum { 148 q0, 149 q1, 150 q2, 151 q3, 152 q4, 153 q5, 154 q6, 155 q7, 156 q8, 157 q9, 158 q10, 159 q11, 160 q12, 161 q13, 162 q14, 163 q15, 164 } FPQuadRegisterID; 165 165 #endif // CPU(ARM_NEON) 166 166 167 inline FPSingleRegisterID asSingle(FPDoubleRegisterID reg)168 {169 ASSERT(reg < d16);170 return (FPSingleRegisterID)(reg << 1);171 }172 173 inline FPDoubleRegisterID asDouble(FPSingleRegisterID reg)174 {175 ASSERT(!(reg & 1));176 return (FPDoubleRegisterID)(reg >> 1);177 }167 inline FPSingleRegisterID asSingle(FPDoubleRegisterID reg) 168 { 169 ASSERT(reg < d16); 170 return (FPSingleRegisterID)(reg << 1); 171 } 172 173 inline FPDoubleRegisterID asDouble(FPSingleRegisterID reg) 174 { 175 ASSERT(!(reg & 1)); 176 return (FPDoubleRegisterID)(reg >> 1); 177 } 178 178 179 179 } // namespace ARMRegisters -
trunk/Source/JavaScriptCore/assembler/MIPSAssembler.h
r224246 r224258 42 42 43 43 namespace MIPSRegisters { 44 45 enum RegisterID : uint8_t { 44 typedef enum { 46 45 r0 = 0, 47 46 r1, … … 108 107 fp = r30, 109 108 ra = r31 110 } ;109 } RegisterID; 111 110 112 111 // Currently, we don't have support for any special purpose registers. 113 enum SPRegisterID : uint8_t{112 typedef enum { 114 113 firstInvalidSPR, 115 114 lastInvalidSPR = -1, 116 } ;117 118 enum FPRegisterID : uint8_t{115 } SPRegisterID; 116 117 typedef enum { 119 118 f0, 120 119 f1, … … 149 148 f30, 150 149 f31 151 } ;150 } FPRegisterID; 152 151 153 152 } // namespace MIPSRegisters -
trunk/Source/JavaScriptCore/assembler/MacroAssembler.h
r224246 r224258 1922 1922 public: 1923 1923 1924 enum RegisterID : uint8_t{ NoRegister };1925 enum FPRegisterID : uint8_t{ NoFPRegister };1924 enum RegisterID { NoRegister }; 1925 enum FPRegisterID { NoFPRegister }; 1926 1926 }; 1927 1927 -
trunk/Source/JavaScriptCore/assembler/X86Assembler.h
r224248 r224258 42 42 namespace X86Registers { 43 43 44 enum RegisterID : uint8_t{44 typedef enum { 45 45 eax, 46 46 ecx, … … 61 61 r15 62 62 #endif 63 } ;64 65 enum SPRegisterID : uint8_t{63 } RegisterID; 64 65 typedef enum { 66 66 eip, 67 67 eflags 68 } ;69 70 enum XMMRegisterID : uint8_t{68 } SPRegisterID; 69 70 typedef enum { 71 71 xmm0, 72 72 xmm1, … … 87 87 xmm15 88 88 #endif 89 } ;89 } XMMRegisterID; 90 90 91 91 } // namespace X86Register … … 104 104 #endif 105 105 } 106 static constexpr unsigned numberOfRegisters() { return static_cast<uint8_t>(lastRegister()) - static_cast<uint8_t>(firstRegister()) + 1; }106 static constexpr unsigned numberOfRegisters() { return lastRegister() - firstRegister() + 1; } 107 107 108 108 typedef X86Registers::SPRegisterID SPRegisterID; … … 110 110 static constexpr SPRegisterID firstSPRegister() { return X86Registers::eip; } 111 111 static constexpr SPRegisterID lastSPRegister() { return X86Registers::eflags; } 112 static constexpr unsigned numberOfSPRegisters() { return static_cast<uint8_t>(lastSPRegister()) - static_cast<uint8_t>(firstSPRegister()) + 1; }112 static constexpr unsigned numberOfSPRegisters() { return lastSPRegister() - firstSPRegister() + 1; } 113 113 114 114 typedef X86Registers::XMMRegisterID XMMRegisterID; … … 124 124 #endif 125 125 } 126 static constexpr unsigned numberOfFPRegisters() { return static_cast<uint8_t>(lastFPRegister()) - static_cast<uint8_t>(firstFPRegister()) + 1; }126 static constexpr unsigned numberOfFPRegisters() { return lastFPRegister() - firstFPRegister() + 1; } 127 127 128 128 static const char* gprName(RegisterID id) -
trunk/Source/JavaScriptCore/bytecode/InlineAccess.cpp
r224243 r224258 162 162 CCallHelpers jit; 163 163 164 GPRReg base = st ubInfo.patch.baseGPR;164 GPRReg base = static_cast<GPRReg>(stubInfo.patch.baseGPR); 165 165 JSValueRegs value = stubInfo.valueRegs(); 166 166 … … 190 190 { 191 191 ScratchRegisterAllocator allocator(stubInfo.patch.usedRegisters); 192 allocator.lock(st ubInfo.patch.baseGPR);193 allocator.lock(st ubInfo.patch.valueGPR);192 allocator.lock(static_cast<GPRReg>(stubInfo.patch.baseGPR)); 193 allocator.lock(static_cast<GPRReg>(stubInfo.patch.valueGPR)); 194 194 #if USE(JSVALUE32_64) 195 allocator.lock(st ubInfo.patch.baseTagGPR);196 allocator.lock(st ubInfo.patch.valueTagGPR);195 allocator.lock(static_cast<GPRReg>(stubInfo.patch.baseTagGPR)); 196 allocator.lock(static_cast<GPRReg>(stubInfo.patch.valueTagGPR)); 197 197 #endif 198 198 GPRReg scratch = allocator.allocateScratchGPR(); -
trunk/Source/JavaScriptCore/bytecode/PolymorphicAccess.cpp
r224243 r224258 380 380 state.ident = &ident; 381 381 382 state.baseGPR = st ubInfo.patch.baseGPR;383 state.thisGPR = st ubInfo.patch.thisGPR;382 state.baseGPR = static_cast<GPRReg>(stubInfo.patch.baseGPR); 383 state.thisGPR = static_cast<GPRReg>(stubInfo.patch.thisGPR); 384 384 state.valueRegs = stubInfo.valueRegs(); 385 385 … … 391 391 allocator.lock(state.valueRegs); 392 392 #if USE(JSVALUE32_64) 393 allocator.lock(st ubInfo.patch.baseTagGPR);393 allocator.lock(static_cast<GPRReg>(stubInfo.patch.baseTagGPR)); 394 394 #endif 395 395 -
trunk/Source/JavaScriptCore/bytecode/StructureStubInfo.h
r224243 r224258 175 175 int32_t deltaFromStartToSlowPathStart; 176 176 177 GPRRegbaseGPR;178 GPRRegvalueGPR;179 GPRRegthisGPR;177 int8_t baseGPR; 178 int8_t valueGPR; 179 int8_t thisGPR; 180 180 #if USE(JSVALUE32_64) 181 GPRRegvalueTagGPR;182 GPRRegbaseTagGPR;183 GPRRegthisTagGPR;181 int8_t valueTagGPR; 182 int8_t baseTagGPR; 183 int8_t thisTagGPR; 184 184 #endif 185 185 } patch; … … 198 198 return JSValueRegs( 199 199 #if USE(JSVALUE32_64) 200 patch.valueTagGPR,200 static_cast<GPRReg>(patch.valueTagGPR), 201 201 #endif 202 patch.valueGPR);202 static_cast<GPRReg>(patch.valueGPR)); 203 203 } 204 204 -
trunk/Source/JavaScriptCore/dfg/DFGSpeculativeJIT.cpp
r224243 r224258 1051 1051 stubInfo->callSiteIndex = m_jit.addCallSite(node->origin.semantic); 1052 1052 stubInfo->codeOrigin = node->origin.semantic; 1053 stubInfo->patch.baseGPR = baseGPR;1054 stubInfo->patch.valueGPR = resultGPR;1055 stubInfo->patch.thisGPR = InvalidGPRReg;1053 stubInfo->patch.baseGPR = static_cast<int8_t>(baseGPR); 1054 stubInfo->patch.valueGPR = static_cast<int8_t>(resultGPR); 1055 stubInfo->patch.thisGPR = static_cast<int8_t>(InvalidGPRReg); 1056 1056 #if USE(JSVALUE32_64) 1057 stubInfo->patch.valueTagGPR = InvalidGPRReg;1058 stubInfo->patch.baseTagGPR = InvalidGPRReg;1059 stubInfo->patch.thisTagGPR = InvalidGPRReg;1057 stubInfo->patch.valueTagGPR = static_cast<int8_t>(InvalidGPRReg); 1058 stubInfo->patch.baseTagGPR = static_cast<int8_t>(InvalidGPRReg); 1059 stubInfo->patch.thisTagGPR = static_cast<int8_t>(InvalidGPRReg); 1060 1060 #endif 1061 1061 stubInfo->patch.usedRegisters = usedRegisters(); -
trunk/Source/JavaScriptCore/ftl/FTLLowerDFGToB3.cpp
r224243 r224258 8865 8865 state->jitCode->common.addCodeOrigin(node->origin.semantic); 8866 8866 stubInfo->codeOrigin = node->origin.semantic; 8867 stubInfo->patch.baseGPR = baseGPR;8868 stubInfo->patch.valueGPR = resultGPR;8869 stubInfo->patch.thisGPR = InvalidGPRReg;8867 stubInfo->patch.baseGPR = static_cast<int8_t>(baseGPR); 8868 stubInfo->patch.valueGPR = static_cast<int8_t>(resultGPR); 8869 stubInfo->patch.thisGPR = static_cast<int8_t>(InvalidGPRReg); 8870 8870 stubInfo->patch.usedRegisters = params.unavailableRegisters(); 8871 8871 -
trunk/Source/JavaScriptCore/jit/JITInlineCacheGenerator.cpp
r224243 r224258 61 61 m_stubInfo->patch.usedRegisters = usedRegisters; 62 62 63 m_stubInfo->patch.baseGPR = base.payloadGPR();64 m_stubInfo->patch.valueGPR = value.payloadGPR();65 m_stubInfo->patch.thisGPR = InvalidGPRReg;63 m_stubInfo->patch.baseGPR = static_cast<int8_t>(base.payloadGPR()); 64 m_stubInfo->patch.valueGPR = static_cast<int8_t>(value.payloadGPR()); 65 m_stubInfo->patch.thisGPR = static_cast<int8_t>(InvalidGPRReg); 66 66 #if USE(JSVALUE32_64) 67 m_stubInfo->patch.baseTagGPR = base.tagGPR();68 m_stubInfo->patch.valueTagGPR = value.tagGPR();69 m_stubInfo->patch.thisTagGPR = InvalidGPRReg;67 m_stubInfo->patch.baseTagGPR = static_cast<int8_t>(base.tagGPR()); 68 m_stubInfo->patch.valueTagGPR = static_cast<int8_t>(value.tagGPR()); 69 m_stubInfo->patch.thisTagGPR = static_cast<int8_t>(InvalidGPRReg); 70 70 #endif 71 71 } … … 126 126 RELEASE_ASSERT(thisRegs.payloadGPR() != thisRegs.tagGPR()); 127 127 128 m_stubInfo->patch.thisGPR = thisRegs.payloadGPR();128 m_stubInfo->patch.thisGPR = static_cast<int8_t>(thisRegs.payloadGPR()); 129 129 #if USE(JSVALUE32_64) 130 m_stubInfo->patch.thisTagGPR = thisRegs.tagGPR();130 m_stubInfo->patch.thisTagGPR = static_cast<int8_t>(thisRegs.tagGPR()); 131 131 #endif 132 132 }
Note: See TracChangeset
for help on using the changeset viewer.