Changeset 225301 in webkit


Ignore:
Timestamp:
Nov 29, 2017 4:16:19 PM (6 years ago)
Author:
clopez@igalia.com
Message:

Source/JavaScriptCore:
[MIPS][JSC] Implement MacroAssembler::probe support on MIPS
​https://bugs.webkit.org/show_bug.cgi?id=175447

Patch by Stanislav Ocovaj <​stanislav.ocovaj@rt-rk.com> on 2017-11-29
Reviewed by Carlos Alberto Lopez Perez.

This patch allows DFG JIT to be enabled on MIPS platforms.

  • Sources.txt:
  • assembler/MIPSAssembler.h:

(JSC::MIPSAssembler::lastSPRegister):
(JSC::MIPSAssembler::numberOfSPRegisters):
(JSC::MIPSAssembler::sprName):

  • assembler/MacroAssemblerMIPS.cpp: Added.

(JSC::MacroAssembler::probe):

  • assembler/ProbeContext.cpp:

(JSC::Probe::executeProbe):

  • assembler/ProbeContext.h:

(JSC::Probe::CPUState::pc):

  • assembler/testmasm.cpp:

(JSC::isSpecialGPR):
(JSC::testProbePreservesGPRS):
(JSC::testProbeModifiesStackPointer):
(JSC::testProbeModifiesStackValues):

Source/WTF:
[DFG][MIPS] Enable DFG JIT on MIPS.
​https://bugs.webkit.org/show_bug.cgi?id=175447

Patch by Stanislav Ocovaj <​stanislav.ocovaj@rt-rk.com> on 2017-11-29
Reviewed by Carlos Alberto Lopez Perez.

  • wtf/Platform.h:
Location:
trunk/Source
Files:
1 added
8 edited

Legend:

Unmodified
Added
Removed

  • trunk/Source/JavaScriptCore/ChangeLog

    • Property svn:executable deleted
    r225293 r225301  
     12017-11-29  Stanislav Ocovaj  <stanislav.ocovaj@rt-rk.com>
     2
     3        [MIPS][JSC] Implement MacroAssembler::probe support on MIPS
     4        https://bugs.webkit.org/show_bug.cgi?id=175447
     5
     6        Reviewed by Carlos Alberto Lopez Perez.
     7
     8        This patch allows DFG JIT to be enabled on MIPS platforms.
     9
     10        * Sources.txt:
     11        * assembler/MIPSAssembler.h:
     12        (JSC::MIPSAssembler::lastSPRegister):
     13        (JSC::MIPSAssembler::numberOfSPRegisters):
     14        (JSC::MIPSAssembler::sprName):
     15        * assembler/MacroAssemblerMIPS.cpp: Added.
     16        (JSC::MacroAssembler::probe):
     17        * assembler/ProbeContext.cpp:
     18        (JSC::Probe::executeProbe):
     19        * assembler/ProbeContext.h:
     20        (JSC::Probe::CPUState::pc):
     21        * assembler/testmasm.cpp:
     22        (JSC::isSpecialGPR):
     23        (JSC::testProbePreservesGPRS):
     24        (JSC::testProbeModifiesStackPointer):
     25        (JSC::testProbeModifiesStackValues):
     26
    1272017-11-29  Matt Lewis  <jlewis3@apple.com>
    228

  • trunk/Source/JavaScriptCore/Sources.txt

    r225293 r225301  
    4848assembler/MacroAssemblerARMv7.cpp
    4949assembler/MacroAssemblerCodeRef.cpp
     50assembler/MacroAssemblerMIPS.cpp
    5051assembler/MacroAssemblerPrinter.cpp
    5152assembler/MacroAssemblerX86Common.cpp

  • trunk/Source/JavaScriptCore/assembler/MIPSAssembler.h

    r225293 r225301  
    114114    fexr = 26,
    115115    fenr = 28,
    116     fcsr = 31
     116    fcsr = 31,
     117    pc
    117118} SPRegisterID;
    118119
    … …  
    166167
    167168    static constexpr SPRegisterID firstSPRegister() { return MIPSRegisters::fir; }
    168     static constexpr SPRegisterID lastSPRegister() { return MIPSRegisters::fcsr; }
    169     static constexpr unsigned numberOfSPRegisters() { return 5; }
     169    static constexpr SPRegisterID lastSPRegister() { return MIPSRegisters::pc; }
     170    static constexpr unsigned numberOfSPRegisters() { return lastSPRegister() - firstSPRegister() + 1; }
    170171
    171172    static constexpr FPRegisterID firstFPRegister() { return MIPSRegisters::f0; }
    … …  
    198199        case MIPSRegisters::fcsr:
    199200            return "fcsr";
     201        case MIPSRegisters::pc:
     202            return "pc";
    200203        default:
    201204            RELEASE_ASSERT_NOT_REACHED();

  • trunk/Source/JavaScriptCore/assembler/ProbeContext.cpp

    r225293 r225301  
    4141    void* originalLR = cpu.gpr<void*>(ARM64Registers::lr);
    4242    void* originalPC = cpu.pc();
     43#elif CPU(MIPS)
     44    auto& cpu = context.cpu;
     45    void* originalRA = cpu.gpr<void*>(MIPSRegisters::ra);
     46    void* originalPC = cpu.pc();
    4347#endif
    4448
    … …  
    5054    // The ARM64 probe trampoline does not support changing both lr and pc.
    5155    RELEASE_ASSERT(originalPC == cpu.pc() || originalLR == cpu.gpr<void*>(ARM64Registers::lr));
     56#elif CPU(MIPS)
     57    // The MIPS probe trampoline does not support changing both ra and pc.
     58    RELEASE_ASSERT(originalPC == cpu.pc() || originalRA == cpu.gpr<void*>(MIPSRegisters::ra));
    5259#endif
    5360

  • trunk/Source/JavaScriptCore/assembler/ProbeContext.h

    r225293 r225301  
    116116    return *reinterpret_cast<void**>(&gpr(ARMRegisters::pc));
    117117#elif CPU(MIPS)
    118     RELEASE_ASSERT_NOT_REACHED();
     118    return *reinterpret_cast<void**>(&spr(MIPSRegisters::pc));
    119119#else
    120120#error "Unsupported CPU"

  • trunk/Source/JavaScriptCore/assembler/testmasm.cpp

    r225293 r225301  
    136136    if (id == ARM64Registers::x18)
    137137        return true;
     138#elif CPU(MIPS)
     139    if (id == MIPSRegisters::zero || id == MIPSRegisters::k0 || id == MIPSRegisters::k1)
     140        return true;
    138141#endif
    139142    return false;
    … …  
    401404            }
    402405            for (auto id = CCallHelpers::firstFPRegister(); id <= CCallHelpers::lastFPRegister(); id = nextID(id))
     406#if CPU(MIPS)
     407                if (!(id & 1))
     408#endif
    403409                CHECK_EQ(cpu.fpr<uint64_t>(id), testWord64(id));
    404410        });
    … …  
    427433            }
    428434            for (auto id = CCallHelpers::firstFPRegister(); id <= CCallHelpers::lastFPRegister(); id = nextID(id))
     435#if CPU(MIPS)
     436                if (!(id & 1))
     437#endif
    429438                CHECK_EQ(cpu.fpr<uint64_t>(id), originalState.fpr<uint64_t>(id));
    430439        });
    … …  
    442451    void* originalSP { nullptr };
    443452    void* modifiedSP { nullptr };
     453#if !(CPU(MIPS))
    444454    uintptr_t modifiedFlags { 0 };
     455#endif
    445456   
    446457#if CPU(X86) || CPU(X86_64)
    … …  
    474485            }
    475486
     487#if !(CPU(MIPS))
    476488            originalState.spr(flagsSPR) = cpu.spr(flagsSPR);
    477489            modifiedFlags = originalState.spr(flagsSPR) ^ flagsMask;
    478490            cpu.spr(flagsSPR) = modifiedFlags;
     491#endif
    479492
    480493            originalSP = cpu.sp();
    … …  
    497510            }
    498511            for (auto id = CCallHelpers::firstFPRegister(); id <= CCallHelpers::lastFPRegister(); id = nextID(id))
     512#if CPU(MIPS)
     513                if (!(id & 1))
     514#endif
    499515                CHECK_EQ(cpu.fpr<uint64_t>(id), testWord64(id));
     516#if !(CPU(MIPS))
    500517            CHECK_EQ(cpu.spr(flagsSPR) & flagsMask, modifiedFlags & flagsMask);
     518#endif
    501519            CHECK_EQ(cpu.sp(), modifiedSP);
    502520        });
    … …  
    513531            for (auto id = CCallHelpers::firstFPRegister(); id <= CCallHelpers::lastFPRegister(); id = nextID(id))
    514532                cpu.fpr(id) = originalState.fpr(id);
     533#if !(CPU(MIPS))
    515534            cpu.spr(flagsSPR) = originalState.spr(flagsSPR);
     535#endif
    516536            cpu.sp() = originalSP;
    517537        });
    … …  
    527547            }
    528548            for (auto id = CCallHelpers::firstFPRegister(); id <= CCallHelpers::lastFPRegister(); id = nextID(id))
     549#if CPU(MIPS)
     550                if (!(id & 1))
     551#endif
    529552                CHECK_EQ(cpu.fpr<uint64_t>(id), originalState.fpr<uint64_t>(id));
     553#if !(CPU(MIPS))
    530554            CHECK_EQ(cpu.spr(flagsSPR) & flagsMask, originalState.spr(flagsSPR) & flagsMask);
     555#endif
    531556            CHECK_EQ(cpu.sp(), originalSP);
    532557        });
    … …  
    641666                cpu.fpr(id) = bitwise_cast<double>(testWord64(id));
    642667            }
     668#if !(CPU(MIPS))
    643669            originalState.spr(flagsSPR) = cpu.spr(flagsSPR);
    644670            modifiedFlags = originalState.spr(flagsSPR) ^ flagsMask;
    645671            cpu.spr(flagsSPR) = modifiedFlags;
     672#endif
    646673
    647674            // Ensure that we'll be writing over the regions of the stack where the Probe::State is.
    … …  
    677704            }
    678705            for (auto id = CCallHelpers::firstFPRegister(); id <= CCallHelpers::lastFPRegister(); id = nextID(id))
     706#if CPU(MIPS)
     707                if (!(id & 1))
     708#endif
    679709                CHECK_EQ(cpu.fpr<uint64_t>(id), testWord64(id));
     710#if !(CPU(MIPS))
    680711            CHECK_EQ(cpu.spr(flagsSPR) & flagsMask, modifiedFlags & flagsMask);
     712#endif
    681713            CHECK_EQ(cpu.sp(), newSP);
    682714
    … …  
    702734            for (auto id = CCallHelpers::firstFPRegister(); id <= CCallHelpers::lastFPRegister(); id = nextID(id))
    703735                cpu.fpr(id) = originalState.fpr(id);
     736#if !(CPU(MIPS))
    704737            cpu.spr(flagsSPR) = originalState.spr(flagsSPR);
     738#endif
    705739            cpu.sp() = originalSP;
    706740        });

  • trunk/Source/WTF/ChangeLog

    • Property svn:executable deleted
    r225293 r225301  
     12017-11-29  Stanislav Ocovaj  <stanislav.ocovaj@rt-rk.com>
     2
     3        [DFG][MIPS] Enable DFG JIT on MIPS.
     4        https://bugs.webkit.org/show_bug.cgi?id=175447
     5
     6        Reviewed by Carlos Alberto Lopez Perez.
     7
     8        * wtf/Platform.h:
     9
    1102017-11-29  Matt Lewis  <jlewis3@apple.com>
    211

  • trunk/Source/WTF/wtf/Platform.h

    r225293 r225301  
    804804#define ENABLE_DFG_JIT 1
    805805#endif
    806 /* FIXME: MIPS cannot enable the DFG until it has support for MacroAssembler::probe().
    807    https://bugs.webkit.org/show_bug.cgi?id=175447
    808 */
     806/* Enable the DFG JIT on MIPS. */
     807#if CPU(MIPS)
     808#define ENABLE_DFG_JIT 1
     809#endif
    809810#endif
    810811
    … …  
    825826#endif
    826827
    827 #if CPU(X86) || CPU(X86_64) || CPU(ARM_THUMB2) || CPU(ARM64) || CPU(ARM_TRADITIONAL)
     828#if CPU(X86) || CPU(X86_64) || CPU(ARM_THUMB2) || CPU(ARM64) || CPU(ARM_TRADITIONAL) || CPU(MIPS)
    828829#define ENABLE_MASM_PROBE 1
    829830#else
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