Changeset 55834 in webkit
- Timestamp:
- Mar 10, 2010 11:53:52 PM (14 years ago)
- Location:
- trunk/JavaScriptCore
- Files:
-
- 3 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/JavaScriptCore/ChangeLog
r55833 r55834 1 2010-03-11 Gabor Loki <loki@webkit.org> 2 3 Reviewed by Gavin Barraclough. 4 5 Buildfix for Thumb-2 after r55684. Add branch8 and branchTest8 functions. 6 https://bugs.webkit.org/show_bug.cgi?id=35892 7 8 * assembler/ARMv7Assembler.h: 9 (JSC::ARMv7Assembler::): 10 (JSC::ARMv7Assembler::ldrb): 11 * assembler/MacroAssemblerARMv7.h: 12 (JSC::MacroAssemblerARMv7::load8): 13 (JSC::MacroAssemblerARMv7::branch8): 14 (JSC::MacroAssemblerARMv7::branchTest8): 15 (JSC::MacroAssemblerARMv7::setTest8): 16 1 17 2010-03-10 Gavin Barraclough <barraclough@apple.com> 2 18 -
trunk/JavaScriptCore/assembler/ARMv7Assembler.h
r55633 r55834 1 1 /* 2 2 * Copyright (C) 2009 Apple Inc. All rights reserved. 3 * Copyright (C) 2010 University of Szeged 3 4 * 4 5 * Redistribution and use in source and binary forms, with or without … … 581 582 OP_BLX = 0x4700, 582 583 OP_BX = 0x4700, 583 OP_LDRH_reg_T1 = 0x5A00,584 584 OP_STR_reg_T1 = 0x5000, 585 585 OP_LDR_reg_T1 = 0x5800, 586 OP_LDRH_reg_T1 = 0x5A00, 587 OP_LDRB_reg_T1 = 0x5C00, 586 588 OP_STR_imm_T1 = 0x6000, 587 589 OP_LDR_imm_T1 = 0x6800, 590 OP_LDRB_imm_T1 = 0x7800, 588 591 OP_LDRH_imm_T1 = 0x8800, 589 592 OP_STR_imm_T2 = 0x9000, … … 630 633 OP_MOVT = 0xF2C0, 631 634 OP_NOP_T2a = 0xF3AF, 635 OP_LDRB_imm_T3 = 0xF810, 636 OP_LDRB_reg_T2 = 0xF810, 632 637 OP_LDRH_reg_T2 = 0xF830, 633 638 OP_LDRH_imm_T3 = 0xF830, … … 636 641 OP_LDR_imm_T4 = 0xF850, 637 642 OP_LDR_reg_T2 = 0xF850, 643 OP_LDRB_imm_T2 = 0xF890, 638 644 OP_LDRH_imm_T2 = 0xF8B0, 639 645 OP_STR_imm_T3 = 0xF8C0, … … 1077 1083 else 1078 1084 m_formatter.twoWordOp12Reg4FourFours(OP_LDRH_reg_T2, rn, FourFours(rt, 0, shift, rm)); 1085 } 1086 1087 void ldrb(RegisterID rt, RegisterID rn, ARMThumbImmediate imm) 1088 { 1089 ASSERT(rn != ARMRegisters::pc); // LDR (literal) 1090 ASSERT(imm.isUInt12()); 1091 1092 if (!((rt | rn) & 8) && imm.isUInt5()) 1093 m_formatter.oneWordOp5Imm5Reg3Reg3(OP_LDRB_imm_T1, imm.getUInt5(), rn, rt); 1094 else 1095 m_formatter.twoWordOp12Reg4Reg4Imm12(OP_LDRB_imm_T2, rn, rt, imm.getUInt12()); 1096 } 1097 1098 void ldrb(RegisterID rt, RegisterID rn, int offset, bool index, bool wback) 1099 { 1100 ASSERT(rt != ARMRegisters::pc); 1101 ASSERT(rn != ARMRegisters::pc); 1102 ASSERT(index || wback); 1103 ASSERT(!wback | (rt != rn)); 1104 1105 bool add = true; 1106 if (offset < 0) { 1107 add = false; 1108 offset = -offset; 1109 } 1110 1111 ASSERT(!(offset & ~0xff)); 1112 1113 offset |= (wback << 8); 1114 offset |= (add << 9); 1115 offset |= (index << 10); 1116 offset |= (1 << 11); 1117 1118 m_formatter.twoWordOp12Reg4Reg4Imm12(OP_LDRB_imm_T3, rn, rt, offset); 1119 } 1120 1121 void ldrb(RegisterID rt, RegisterID rn, RegisterID rm, unsigned shift = 0) 1122 { 1123 ASSERT(rn != ARMRegisters::pc); // LDR (literal) 1124 ASSERT(!BadReg(rm)); 1125 ASSERT(shift <= 3); 1126 1127 if (!shift && !((rt | rn | rm) & 8)) 1128 m_formatter.oneWordOp7Reg3Reg3Reg3(OP_LDRB_reg_T1, rm, rn, rt); 1129 else 1130 m_formatter.twoWordOp12Reg4FourFours(OP_LDRB_reg_T2, rn, FourFours(rt, 0, shift, rm)); 1079 1131 } 1080 1132 -
trunk/JavaScriptCore/assembler/MacroAssemblerARMv7.h
r55633 r55834 1 1 /* 2 2 * Copyright (C) 2009 Apple Inc. All rights reserved. 3 * Copyright (C) 2010 University of Szeged 3 4 * 4 5 * Redistribution and use in source and binary forms, with or without … … 367 368 } 368 369 370 void load8(ArmAddress address, RegisterID dest) 371 { 372 if (address.type == ArmAddress::HasIndex) 373 m_assembler.ldrb(dest, address.base, address.u.index, address.u.scale); 374 else if (address.u.offset >= 0) { 375 ARMThumbImmediate armImm = ARMThumbImmediate::makeUInt12(address.u.offset); 376 ASSERT(armImm.isValid()); 377 m_assembler.ldrb(dest, address.base, armImm); 378 } else { 379 ASSERT(address.u.offset >= -255); 380 m_assembler.ldrb(dest, address.base, address.u.offset, true, false); 381 } 382 } 383 369 384 void store32(RegisterID src, ArmAddress address) 370 385 { … … 401 416 move(ImmPtr(address), addressTempRegister); 402 417 m_assembler.ldr(dest, addressTempRegister, ARMThumbImmediate::makeUInt16(0)); 418 } 419 420 void load8(ImplicitAddress address, RegisterID dest) 421 { 422 load8(setupArmAddress(address), dest); 403 423 } 404 424 … … 792 812 } 793 813 814 Jump branch8(Condition cond, RegisterID left, Imm32 right) 815 { 816 compare32(left, right); 817 return Jump(makeBranch(cond)); 818 } 819 820 Jump branch8(Condition cond, Address left, Imm32 right) 821 { 822 // use addressTempRegister incase the branch8 we call uses dataTempRegister. :-/ 823 load8(left, addressTempRegister); 824 return branch8(cond, addressTempRegister, right); 825 } 826 794 827 Jump branchTest32(Condition cond, RegisterID reg, RegisterID mask) 795 828 { … … 820 853 load32(address, addressTempRegister); 821 854 return branchTest32(cond, addressTempRegister, mask); 855 } 856 857 Jump branchTest8(Condition cond, RegisterID reg, Imm32 mask = Imm32(-1)) 858 { 859 ASSERT((cond == Zero) || (cond == NonZero)); 860 test32(reg, mask); 861 return Jump(makeBranch(cond)); 862 } 863 864 Jump branchTest8(Condition cond, Address address, Imm32 mask = Imm32(-1)) 865 { 866 ASSERT((cond == Zero) || (cond == NonZero)); 867 // use addressTempRegister incase the branchTest8 we call uses dataTempRegister. :-/ 868 load8(address, addressTempRegister); 869 return branchTest8(cond, addressTempRegister, mask); 822 870 } 823 871 … … 972 1020 } 973 1021 1022 void setTest8(Condition cond, Address address, Imm32 mask, RegisterID dest) 1023 { 1024 load8(address, dataTempRegister); 1025 test32(dataTempRegister, mask); 1026 m_assembler.it(armV7Condition(cond), false); 1027 m_assembler.mov(dest, ARMThumbImmediate::makeUInt16(1)); 1028 m_assembler.mov(dest, ARMThumbImmediate::makeUInt16(0)); 1029 } 974 1030 975 1031 DataLabel32 moveWithPatch(Imm32 imm, RegisterID dst)
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