Changeset 58091 in webkit
- Timestamp:
- Apr 22, 2010 6:24:56 AM (14 years ago)
- Location:
- trunk/JavaScriptCore
- Files:
-
- 4 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/JavaScriptCore/ChangeLog
r58045 r58091 1 2010-04-22 Gabor Loki <loki@webkit.org> 2 3 Reviewed by Gavin Barraclough. 4 5 Use BLX and BX to keep happy the return stack predictor above ARMv4 6 https://bugs.webkit.org/show_bug.cgi?id=37862 7 8 Inspired by Jacob Bramley's patch from JaegerMonkey 9 10 * assembler/ARMAssembler.cpp: 11 (JSC::ARMAssembler::executableCopy): 12 * assembler/ARMAssembler.h: 13 (JSC::ARMAssembler::): 14 (JSC::ARMAssembler::bx): 15 (JSC::ARMAssembler::blx): 16 (JSC::ARMAssembler::loadBranchTarget): 17 (JSC::ARMAssembler::jmp): 18 (JSC::ARMAssembler::getLdrImmAddress): 19 * assembler/MacroAssemblerARM.h: 20 (JSC::MacroAssemblerARM::jump): 21 (JSC::MacroAssemblerARM::nearCall): 22 (JSC::MacroAssemblerARM::call): 23 (JSC::MacroAssemblerARM::ret): 24 (JSC::MacroAssemblerARM::prepareCall): 25 (JSC::MacroAssemblerARM::call32): 26 1 27 2010-04-21 Andy Estes <aestes@apple.com> 2 28 -
trunk/JavaScriptCore/assembler/ARMAssembler.cpp
r55718 r58091 358 358 ARMWord* ldrAddr = reinterpret_cast<ARMWord*>(data + pos); 359 359 ARMWord* addr = getLdrImmAddress(ldrAddr); 360 if (*addr != 0xffffffff) {360 if (*addr != InvalidBranchTarget) { 361 361 if (!(*iter & 1)) { 362 362 int diff = reinterpret_cast<ARMWord*>(data + *addr) - (ldrAddr + DefaultPrefetching); -
trunk/JavaScriptCore/assembler/ARMAssembler.h
r55718 r58091 1 1 /* 2 * Copyright (C) 2009 University of Szeged2 * Copyright (C) 2009, 2010 University of Szeged 3 3 * All rights reserved. 4 4 * … … 132 132 B = 0x0a000000, 133 133 BL = 0x0b000000, 134 #if WTF_ARM_ARCH_AT_LEAST(5) || defined(__ARM_ARCH_4T__) 135 BX = 0x012fff10, 136 #endif 134 137 FMSR = 0x0e000a10, 135 138 FMRS = 0x0e100a10, … … 140 143 CLZ = 0x016f0f10, 141 144 BKPT = 0xe120070, 145 BLX = 0x012fff30, 142 146 #endif 143 147 #if WTF_ARM_ARCH_AT_LEAST(7) … … 183 187 184 188 static const ARMWord INVALID_IMM = 0xf0000000; 189 static const ARMWord InvalidBranchTarget = 0xffffffff; 185 190 static const int DefaultPrefetching = 2; 186 191 … … 548 553 } 549 554 555 void bx(int rm, Condition cc = AL) 556 { 557 #if WTF_ARM_ARCH_AT_LEAST(5) || defined(__ARM_ARCH_4T__) 558 emitInst(static_cast<ARMWord>(cc) | BX, 0, 0, RM(rm)); 559 #else 560 mov_r(ARMRegisters::pc, RM(rm), cc); 561 #endif 562 } 563 564 JmpSrc blx(int rm, Condition cc = AL) 565 { 566 #if WTF_ARM_ARCH_AT_LEAST(5) 567 int s = m_buffer.uncheckedSize(); 568 emitInst(static_cast<ARMWord>(cc) | BLX, 0, 0, RM(rm)); 569 #else 570 ASSERT(rm != 14); 571 ensureSpace(2 * sizeof(ARMWord), 0); 572 mov_r(ARMRegisters::lr, ARMRegisters::pc, cc); 573 int s = m_buffer.uncheckedSize(); 574 bx(rm, cc); 575 #endif 576 return JmpSrc(s); 577 } 578 550 579 static ARMWord lsl(int reg, ARMWord value) 551 580 { … … 620 649 } 621 650 622 JmpSrc jmp(Condition cc = AL, int useConstantPool = 0)651 JmpSrc loadBranchTarget(int rd, Condition cc = AL, int useConstantPool = 0) 623 652 { 624 653 ensureSpace(sizeof(ARMWord), sizeof(ARMWord)); 625 654 int s = m_buffer.uncheckedSize(); 626 ldr_un_imm( ARMRegisters::pc, 0xffffffff, cc);655 ldr_un_imm(rd, InvalidBranchTarget, cc); 627 656 m_jumps.append(s | (useConstantPool & 0x1)); 628 657 return JmpSrc(s); 629 658 } 630 659 660 JmpSrc jmp(Condition cc = AL, int useConstantPool = 0) 661 { 662 return loadBranchTarget(ARMRegisters::pc, cc, useConstantPool); 663 } 664 631 665 void* executableCopy(ExecutablePool* allocator); 632 666 … … 635 669 static ARMWord* getLdrImmAddress(ARMWord* insn) 636 670 { 671 #if WTF_ARM_ARCH_AT_LEAST(5) 672 // Check for call 673 if ((*insn & 0x0f7f0000) != 0x051f0000) { 674 // Must be BLX 675 ASSERT((*insn & 0x012fff30) == 0x012fff30); 676 insn--; 677 } 678 #endif 637 679 // Must be an ldr ..., [pc +/- imm] 638 680 ASSERT((*insn & 0x0f7f0000) == 0x051f0000); -
trunk/JavaScriptCore/assembler/MacroAssemblerARM.h
r56348 r58091 1 1 /* 2 2 * Copyright (C) 2008 Apple Inc. 3 * Copyright (C) 2009 University of Szeged3 * Copyright (C) 2009, 2010 University of Szeged 4 4 * All rights reserved. 5 5 * … … 475 475 void jump(RegisterID target) 476 476 { 477 m ove(target, ARMRegisters::pc);477 m_assembler.bx(target); 478 478 } 479 479 … … 567 567 Call nearCall() 568 568 { 569 #if WTF_ARM_ARCH_AT_LEAST(5) 570 ensureSpace(2 * sizeof(ARMWord), sizeof(ARMWord)); 571 m_assembler.loadBranchTarget(ARMRegisters::S1, ARMAssembler::AL, true); 572 return Call(m_assembler.blx(ARMRegisters::S1), Call::LinkableNear); 573 #else 569 574 prepareCall(); 570 575 return Call(m_assembler.jmp(ARMAssembler::AL, true), Call::LinkableNear); 576 #endif 571 577 } 572 578 573 579 Call call(RegisterID target) 574 580 { 575 prepareCall(); 576 move(ARMRegisters::pc, target); 581 m_assembler.blx(target); 577 582 JmpSrc jmpSrc; 578 583 return Call(jmpSrc, Call::None); … … 586 591 void ret() 587 592 { 588 m_assembler. mov_r(ARMRegisters::pc,linkRegister);593 m_assembler.bx(linkRegister); 589 594 } 590 595 … … 682 687 Call call() 683 688 { 689 #if WTF_ARM_ARCH_AT_LEAST(5) 690 ensureSpace(2 * sizeof(ARMWord), sizeof(ARMWord)); 691 m_assembler.loadBranchTarget(ARMRegisters::S1, ARMAssembler::AL, true); 692 return Call(m_assembler.blx(ARMRegisters::S1), Call::Linkable); 693 #else 684 694 prepareCall(); 685 695 return Call(m_assembler.jmp(ARMAssembler::AL, true), Call::Linkable); 696 #endif 686 697 } 687 698 … … 887 898 void prepareCall() 888 899 { 900 #if WTF_ARM_ARCH_VERSION < 5 889 901 ensureSpace(2 * sizeof(ARMWord), sizeof(ARMWord)); 890 902 891 903 m_assembler.mov_r(linkRegister, ARMRegisters::pc); 904 #endif 892 905 } 893 906 894 907 void call32(RegisterID base, int32_t offset) 895 908 { 909 #if WTF_ARM_ARCH_AT_LEAST(5) 910 int targetReg = ARMRegisters::S1; 911 #else 912 int targetReg = ARMRegisters::pc; 913 #endif 914 int tmpReg = ARMRegisters::S1; 915 896 916 if (base == ARMRegisters::sp) 897 917 offset += 4; … … 900 920 if (offset <= 0xfff) { 901 921 prepareCall(); 902 m_assembler.dtr_u(true, ARMRegisters::pc, base, offset);922 m_assembler.dtr_u(true, targetReg, base, offset); 903 923 } else if (offset <= 0xfffff) { 904 m_assembler.add_r( ARMRegisters::S0, base, ARMAssembler::OP2_IMM | (offset >> 12) | (10 << 8));924 m_assembler.add_r(tmpReg, base, ARMAssembler::OP2_IMM | (offset >> 12) | (10 << 8)); 905 925 prepareCall(); 906 m_assembler.dtr_u(true, ARMRegisters::pc, ARMRegisters::S0, offset & 0xfff);926 m_assembler.dtr_u(true, targetReg, tmpReg, offset & 0xfff); 907 927 } else { 908 ARMWord reg = m_assembler.getImm(offset, ARMRegisters::S0);928 ARMWord reg = m_assembler.getImm(offset, tmpReg); 909 929 prepareCall(); 910 m_assembler.dtr_ur(true, ARMRegisters::pc, base, reg);930 m_assembler.dtr_ur(true, targetReg, base, reg); 911 931 } 912 932 } else { … … 914 934 if (offset <= 0xfff) { 915 935 prepareCall(); 916 m_assembler.dtr_d(true, ARMRegisters::pc, base, offset);936 m_assembler.dtr_d(true, targetReg, base, offset); 917 937 } else if (offset <= 0xfffff) { 918 m_assembler.sub_r( ARMRegisters::S0, base, ARMAssembler::OP2_IMM | (offset >> 12) | (10 << 8));938 m_assembler.sub_r(tmpReg, base, ARMAssembler::OP2_IMM | (offset >> 12) | (10 << 8)); 919 939 prepareCall(); 920 m_assembler.dtr_d(true, ARMRegisters::pc, ARMRegisters::S0, offset & 0xfff);940 m_assembler.dtr_d(true, targetReg, tmpReg, offset & 0xfff); 921 941 } else { 922 ARMWord reg = m_assembler.getImm(offset, ARMRegisters::S0);942 ARMWord reg = m_assembler.getImm(offset, tmpReg); 923 943 prepareCall(); 924 m_assembler.dtr_dr(true, ARMRegisters::pc, base, reg);944 m_assembler.dtr_dr(true, targetReg, base, reg); 925 945 } 926 946 } 947 #if WTF_ARM_ARCH_AT_LEAST(5) 948 m_assembler.blx(targetReg); 949 #endif 927 950 } 928 951
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