Changeset 90426 in webkit
- Timestamp:
- Jul 5, 2011 6:30:53 PM (13 years ago)
- Location:
- trunk/Source/JavaScriptCore
- Files:
-
- 4 edited
-
ChangeLog (modified) (1 diff)
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assembler/ARMv7Assembler.h (modified) (66 diffs)
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assembler/LinkBuffer.h (modified) (1 diff)
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assembler/MacroAssemblerARMv7.h (modified) (14 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/Source/JavaScriptCore/ChangeLog
r90425 r90426 1 2011-07-05 Oliver Hunt <oliver@apple.com> 2 3 Force inlining of simple functions that show up as not being inlined 4 https://bugs.webkit.org/show_bug.cgi?id=63964 5 6 Reviewed by Gavin Barraclough. 7 8 Looking at profile data indicates the gcc is failing to inline a 9 number of trivial functions. This patch hits the ones that show 10 up in profiles with the ALWAYS_INLINE hammer. 11 12 We also replace the memcpy() call in linking with a manual loop. 13 Apparently memcpy() is almost never faster than an inlined loop. 14 15 * assembler/ARMv7Assembler.h: 16 (JSC::ARMv7Assembler::add): 17 (JSC::ARMv7Assembler::add_S): 18 (JSC::ARMv7Assembler::ARM_and): 19 (JSC::ARMv7Assembler::asr): 20 (JSC::ARMv7Assembler::b): 21 (JSC::ARMv7Assembler::blx): 22 (JSC::ARMv7Assembler::bx): 23 (JSC::ARMv7Assembler::clz): 24 (JSC::ARMv7Assembler::cmn): 25 (JSC::ARMv7Assembler::cmp): 26 (JSC::ARMv7Assembler::eor): 27 (JSC::ARMv7Assembler::it): 28 (JSC::ARMv7Assembler::ldr): 29 (JSC::ARMv7Assembler::ldrCompact): 30 (JSC::ARMv7Assembler::ldrh): 31 (JSC::ARMv7Assembler::ldrb): 32 (JSC::ARMv7Assembler::lsl): 33 (JSC::ARMv7Assembler::lsr): 34 (JSC::ARMv7Assembler::movT3): 35 (JSC::ARMv7Assembler::mov): 36 (JSC::ARMv7Assembler::movt): 37 (JSC::ARMv7Assembler::mvn): 38 (JSC::ARMv7Assembler::neg): 39 (JSC::ARMv7Assembler::orr): 40 (JSC::ARMv7Assembler::orr_S): 41 (JSC::ARMv7Assembler::ror): 42 (JSC::ARMv7Assembler::smull): 43 (JSC::ARMv7Assembler::str): 44 (JSC::ARMv7Assembler::sub): 45 (JSC::ARMv7Assembler::sub_S): 46 (JSC::ARMv7Assembler::tst): 47 (JSC::ARMv7Assembler::linkRecordSourceComparator): 48 (JSC::ARMv7Assembler::link): 49 (JSC::ARMv7Assembler::ARMInstructionFormatter::oneWordOp5Reg3Imm8): 50 (JSC::ARMv7Assembler::ARMInstructionFormatter::oneWordOp5Imm5Reg3Reg3): 51 (JSC::ARMv7Assembler::ARMInstructionFormatter::oneWordOp7Reg3Reg3Reg3): 52 (JSC::ARMv7Assembler::ARMInstructionFormatter::oneWordOp8Imm8): 53 (JSC::ARMv7Assembler::ARMInstructionFormatter::oneWordOp8RegReg143): 54 (JSC::ARMv7Assembler::ARMInstructionFormatter::oneWordOp9Imm7): 55 (JSC::ARMv7Assembler::ARMInstructionFormatter::oneWordOp10Reg3Reg3): 56 (JSC::ARMv7Assembler::ARMInstructionFormatter::twoWordOp12Reg4FourFours): 57 (JSC::ARMv7Assembler::ARMInstructionFormatter::twoWordOp16FourFours): 58 (JSC::ARMv7Assembler::ARMInstructionFormatter::twoWordOp16Op16): 59 (JSC::ARMv7Assembler::ARMInstructionFormatter::twoWordOp5i6Imm4Reg4EncodedImm): 60 (JSC::ARMv7Assembler::ARMInstructionFormatter::twoWordOp12Reg4Reg4Imm12): 61 (JSC::ARMv7Assembler::ARMInstructionFormatter::vfpOp): 62 (JSC::ARMv7Assembler::ARMInstructionFormatter::vfpMemOp): 63 * assembler/LinkBuffer.h: 64 (JSC::LinkBuffer::linkCode): 65 * assembler/MacroAssemblerARMv7.h: 66 (JSC::MacroAssemblerARMv7::nearCall): 67 (JSC::MacroAssemblerARMv7::call): 68 (JSC::MacroAssemblerARMv7::ret): 69 (JSC::MacroAssemblerARMv7::moveWithPatch): 70 (JSC::MacroAssemblerARMv7::branchPtrWithPatch): 71 (JSC::MacroAssemblerARMv7::storePtrWithPatch): 72 (JSC::MacroAssemblerARMv7::tailRecursiveCall): 73 (JSC::MacroAssemblerARMv7::makeTailRecursiveCall): 74 (JSC::MacroAssemblerARMv7::jump): 75 (JSC::MacroAssemblerARMv7::makeBranch): 76 1 77 2011-07-05 Zoltan Herczeg <zherczeg@inf.u-szeged.hu> 2 78 -
trunk/Source/JavaScriptCore/assembler/ARMv7Assembler.h
r89729 r90426 720 720 } 721 721 722 void add(RegisterID rd, RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift)722 ALWAYS_INLINE void add(RegisterID rd, RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift) 723 723 { 724 724 ASSERT((rd != ARMRegisters::sp) || (rn == ARMRegisters::sp)); … … 730 730 731 731 // NOTE: In an IT block, add doesn't modify the flags register. 732 void add(RegisterID rd, RegisterID rn, RegisterID rm)732 ALWAYS_INLINE void add(RegisterID rd, RegisterID rn, RegisterID rm) 733 733 { 734 734 if (rd == rn) … … 743 743 744 744 // Not allowed in an IT (if then) block. 745 void add_S(RegisterID rd, RegisterID rn, ARMThumbImmediate imm)745 ALWAYS_INLINE void add_S(RegisterID rd, RegisterID rn, ARMThumbImmediate imm) 746 746 { 747 747 // Rd can only be SP if Rn is also SP. … … 765 765 766 766 // Not allowed in an IT (if then) block? 767 void add_S(RegisterID rd, RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift)767 ALWAYS_INLINE void add_S(RegisterID rd, RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift) 768 768 { 769 769 ASSERT((rd != ARMRegisters::sp) || (rn == ARMRegisters::sp)); … … 775 775 776 776 // Not allowed in an IT (if then) block. 777 void add_S(RegisterID rd, RegisterID rn, RegisterID rm)777 ALWAYS_INLINE void add_S(RegisterID rd, RegisterID rn, RegisterID rm) 778 778 { 779 779 if (!((rd | rn | rm) & 8)) … … 783 783 } 784 784 785 void ARM_and(RegisterID rd, RegisterID rn, ARMThumbImmediate imm)785 ALWAYS_INLINE void ARM_and(RegisterID rd, RegisterID rn, ARMThumbImmediate imm) 786 786 { 787 787 ASSERT(!BadReg(rd)); … … 791 791 } 792 792 793 void ARM_and(RegisterID rd, RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift)793 ALWAYS_INLINE void ARM_and(RegisterID rd, RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift) 794 794 { 795 795 ASSERT(!BadReg(rd)); … … 799 799 } 800 800 801 void ARM_and(RegisterID rd, RegisterID rn, RegisterID rm)801 ALWAYS_INLINE void ARM_and(RegisterID rd, RegisterID rn, RegisterID rm) 802 802 { 803 803 if ((rd == rn) && !((rd | rm) & 8)) … … 809 809 } 810 810 811 void asr(RegisterID rd, RegisterID rm, int32_t shiftAmount)811 ALWAYS_INLINE void asr(RegisterID rd, RegisterID rm, int32_t shiftAmount) 812 812 { 813 813 ASSERT(!BadReg(rd)); … … 817 817 } 818 818 819 void asr(RegisterID rd, RegisterID rn, RegisterID rm)819 ALWAYS_INLINE void asr(RegisterID rd, RegisterID rn, RegisterID rm) 820 820 { 821 821 ASSERT(!BadReg(rd)); … … 826 826 827 827 // Only allowed in IT (if then) block if last instruction. 828 A ssemblerLabel b()828 ALWAYS_INLINE AssemblerLabel b() 829 829 { 830 830 m_formatter.twoWordOp16Op16(OP_B_T4a, OP_B_T4b); … … 833 833 834 834 // Only allowed in IT (if then) block if last instruction. 835 A ssemblerLabel blx(RegisterID rm)835 ALWAYS_INLINE AssemblerLabel blx(RegisterID rm) 836 836 { 837 837 ASSERT(rm != ARMRegisters::pc); … … 841 841 842 842 // Only allowed in IT (if then) block if last instruction. 843 A ssemblerLabel bx(RegisterID rm)843 ALWAYS_INLINE AssemblerLabel bx(RegisterID rm) 844 844 { 845 845 m_formatter.oneWordOp8RegReg143(OP_BX, rm, (RegisterID)0); … … 852 852 } 853 853 854 void clz(RegisterID rd, RegisterID rm)854 ALWAYS_INLINE void clz(RegisterID rd, RegisterID rm) 855 855 { 856 856 ASSERT(!BadReg(rd)); … … 859 859 } 860 860 861 void cmn(RegisterID rn, ARMThumbImmediate imm)861 ALWAYS_INLINE void cmn(RegisterID rn, ARMThumbImmediate imm) 862 862 { 863 863 ASSERT(rn != ARMRegisters::pc); … … 867 867 } 868 868 869 void cmp(RegisterID rn, ARMThumbImmediate imm)869 ALWAYS_INLINE void cmp(RegisterID rn, ARMThumbImmediate imm) 870 870 { 871 871 ASSERT(rn != ARMRegisters::pc); … … 878 878 } 879 879 880 void cmp(RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift)880 ALWAYS_INLINE void cmp(RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift) 881 881 { 882 882 ASSERT(rn != ARMRegisters::pc); … … 885 885 } 886 886 887 void cmp(RegisterID rn, RegisterID rm)887 ALWAYS_INLINE void cmp(RegisterID rn, RegisterID rm) 888 888 { 889 889 if ((rn | rm) & 8) … … 894 894 895 895 // xor is not spelled with an 'e'. :-( 896 void eor(RegisterID rd, RegisterID rn, ARMThumbImmediate imm)896 ALWAYS_INLINE void eor(RegisterID rd, RegisterID rn, ARMThumbImmediate imm) 897 897 { 898 898 ASSERT(!BadReg(rd)); … … 903 903 904 904 // xor is not spelled with an 'e'. :-( 905 void eor(RegisterID rd, RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift)905 ALWAYS_INLINE void eor(RegisterID rd, RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift) 906 906 { 907 907 ASSERT(!BadReg(rd)); … … 922 922 } 923 923 924 void it(Condition cond)924 ALWAYS_INLINE void it(Condition cond) 925 925 { 926 926 m_formatter.oneWordOp8Imm8(OP_IT, ifThenElse(cond)); 927 927 } 928 928 929 void it(Condition cond, bool inst2if)929 ALWAYS_INLINE void it(Condition cond, bool inst2if) 930 930 { 931 931 m_formatter.oneWordOp8Imm8(OP_IT, ifThenElse(cond, inst2if)); 932 932 } 933 933 934 void it(Condition cond, bool inst2if, bool inst3if)934 ALWAYS_INLINE void it(Condition cond, bool inst2if, bool inst3if) 935 935 { 936 936 m_formatter.oneWordOp8Imm8(OP_IT, ifThenElse(cond, inst2if, inst3if)); 937 937 } 938 938 939 void it(Condition cond, bool inst2if, bool inst3if, bool inst4if)939 ALWAYS_INLINE void it(Condition cond, bool inst2if, bool inst3if, bool inst4if) 940 940 { 941 941 m_formatter.oneWordOp8Imm8(OP_IT, ifThenElse(cond, inst2if, inst3if, inst4if)); … … 943 943 944 944 // rt == ARMRegisters::pc only allowed if last instruction in IT (if then) block. 945 void ldr(RegisterID rt, RegisterID rn, ARMThumbImmediate imm)945 ALWAYS_INLINE void ldr(RegisterID rt, RegisterID rn, ARMThumbImmediate imm) 946 946 { 947 947 ASSERT(rn != ARMRegisters::pc); // LDR (literal) … … 956 956 } 957 957 958 void ldrCompact(RegisterID rt, RegisterID rn, ARMThumbImmediate imm)958 ALWAYS_INLINE void ldrCompact(RegisterID rt, RegisterID rn, ARMThumbImmediate imm) 959 959 { 960 960 ASSERT(rn != ARMRegisters::pc); // LDR (literal) … … 975 975 // MEM[index ? _tmp : _reg] = REG[rt] 976 976 // if (wback) REG[rn] = _tmp 977 void ldr(RegisterID rt, RegisterID rn, int offset, bool index, bool wback)977 ALWAYS_INLINE void ldr(RegisterID rt, RegisterID rn, int offset, bool index, bool wback) 978 978 { 979 979 ASSERT(rt != ARMRegisters::pc); … … 998 998 999 999 // rt == ARMRegisters::pc only allowed if last instruction in IT (if then) block. 1000 void ldr(RegisterID rt, RegisterID rn, RegisterID rm, unsigned shift=0)1000 ALWAYS_INLINE void ldr(RegisterID rt, RegisterID rn, RegisterID rm, unsigned shift = 0) 1001 1001 { 1002 1002 ASSERT(rn != ARMRegisters::pc); // LDR (literal) … … 1011 1011 1012 1012 // rt == ARMRegisters::pc only allowed if last instruction in IT (if then) block. 1013 void ldrh(RegisterID rt, RegisterID rn, ARMThumbImmediate imm)1013 ALWAYS_INLINE void ldrh(RegisterID rt, RegisterID rn, ARMThumbImmediate imm) 1014 1014 { 1015 1015 ASSERT(rn != ARMRegisters::pc); // LDR (literal) … … 1033 1033 // MEM[index ? _tmp : _reg] = REG[rt] 1034 1034 // if (wback) REG[rn] = _tmp 1035 void ldrh(RegisterID rt, RegisterID rn, int offset, bool index, bool wback)1035 ALWAYS_INLINE void ldrh(RegisterID rt, RegisterID rn, int offset, bool index, bool wback) 1036 1036 { 1037 1037 ASSERT(rt != ARMRegisters::pc); … … 1055 1055 } 1056 1056 1057 void ldrh(RegisterID rt, RegisterID rn, RegisterID rm, unsigned shift=0)1057 ALWAYS_INLINE void ldrh(RegisterID rt, RegisterID rn, RegisterID rm, unsigned shift = 0) 1058 1058 { 1059 1059 ASSERT(!BadReg(rt)); // Memory hint … … 1102 1102 } 1103 1103 1104 void ldrb(RegisterID rt, RegisterID rn, RegisterID rm, unsigned shift = 0)1104 ALWAYS_INLINE void ldrb(RegisterID rt, RegisterID rn, RegisterID rm, unsigned shift = 0) 1105 1105 { 1106 1106 ASSERT(rn != ARMRegisters::pc); // LDR (literal) … … 1122 1122 } 1123 1123 1124 void lsl(RegisterID rd, RegisterID rn, RegisterID rm)1124 ALWAYS_INLINE void lsl(RegisterID rd, RegisterID rn, RegisterID rm) 1125 1125 { 1126 1126 ASSERT(!BadReg(rd)); … … 1130 1130 } 1131 1131 1132 void lsr(RegisterID rd, RegisterID rm, int32_t shiftAmount)1132 ALWAYS_INLINE void lsr(RegisterID rd, RegisterID rm, int32_t shiftAmount) 1133 1133 { 1134 1134 ASSERT(!BadReg(rd)); … … 1138 1138 } 1139 1139 1140 void lsr(RegisterID rd, RegisterID rn, RegisterID rm)1140 ALWAYS_INLINE void lsr(RegisterID rd, RegisterID rn, RegisterID rm) 1141 1141 { 1142 1142 ASSERT(!BadReg(rd)); … … 1146 1146 } 1147 1147 1148 void movT3(RegisterID rd, ARMThumbImmediate imm)1148 ALWAYS_INLINE void movT3(RegisterID rd, ARMThumbImmediate imm) 1149 1149 { 1150 1150 ASSERT(imm.isValid()); … … 1155 1155 } 1156 1156 1157 void mov(RegisterID rd, ARMThumbImmediate imm)1157 ALWAYS_INLINE void mov(RegisterID rd, ARMThumbImmediate imm) 1158 1158 { 1159 1159 ASSERT(imm.isValid()); … … 1168 1168 } 1169 1169 1170 void mov(RegisterID rd, RegisterID rm)1170 ALWAYS_INLINE void mov(RegisterID rd, RegisterID rm) 1171 1171 { 1172 1172 m_formatter.oneWordOp8RegReg143(OP_MOV_reg_T1, rm, rd); 1173 1173 } 1174 1174 1175 void movt(RegisterID rd, ARMThumbImmediate imm)1175 ALWAYS_INLINE void movt(RegisterID rd, ARMThumbImmediate imm) 1176 1176 { 1177 1177 ASSERT(imm.isUInt16()); … … 1180 1180 } 1181 1181 1182 void mvn(RegisterID rd, ARMThumbImmediate imm)1182 ALWAYS_INLINE void mvn(RegisterID rd, ARMThumbImmediate imm) 1183 1183 { 1184 1184 ASSERT(imm.isEncodedImm()); … … 1188 1188 } 1189 1189 1190 void mvn(RegisterID rd, RegisterID rm, ShiftTypeAndAmount shift)1190 ALWAYS_INLINE void mvn(RegisterID rd, RegisterID rm, ShiftTypeAndAmount shift) 1191 1191 { 1192 1192 ASSERT(!BadReg(rd)); … … 1195 1195 } 1196 1196 1197 void mvn(RegisterID rd, RegisterID rm)1197 ALWAYS_INLINE void mvn(RegisterID rd, RegisterID rm) 1198 1198 { 1199 1199 if (!((rd | rm) & 8)) … … 1203 1203 } 1204 1204 1205 void neg(RegisterID rd, RegisterID rm)1205 ALWAYS_INLINE void neg(RegisterID rd, RegisterID rm) 1206 1206 { 1207 1207 ARMThumbImmediate zero = ARMThumbImmediate::makeUInt12(0); … … 1209 1209 } 1210 1210 1211 void orr(RegisterID rd, RegisterID rn, ARMThumbImmediate imm)1211 ALWAYS_INLINE void orr(RegisterID rd, RegisterID rn, ARMThumbImmediate imm) 1212 1212 { 1213 1213 ASSERT(!BadReg(rd)); … … 1217 1217 } 1218 1218 1219 void orr(RegisterID rd, RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift)1219 ALWAYS_INLINE void orr(RegisterID rd, RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift) 1220 1220 { 1221 1221 ASSERT(!BadReg(rd)); … … 1235 1235 } 1236 1236 1237 void orr_S(RegisterID rd, RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift)1237 ALWAYS_INLINE void orr_S(RegisterID rd, RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift) 1238 1238 { 1239 1239 ASSERT(!BadReg(rd)); … … 1253 1253 } 1254 1254 1255 void ror(RegisterID rd, RegisterID rm, int32_t shiftAmount)1255 ALWAYS_INLINE void ror(RegisterID rd, RegisterID rm, int32_t shiftAmount) 1256 1256 { 1257 1257 ASSERT(!BadReg(rd)); … … 1261 1261 } 1262 1262 1263 void ror(RegisterID rd, RegisterID rn, RegisterID rm)1263 ALWAYS_INLINE void ror(RegisterID rd, RegisterID rn, RegisterID rm) 1264 1264 { 1265 1265 ASSERT(!BadReg(rd)); … … 1269 1269 } 1270 1270 1271 void smull(RegisterID rdLo, RegisterID rdHi, RegisterID rn, RegisterID rm)1271 ALWAYS_INLINE void smull(RegisterID rdLo, RegisterID rdHi, RegisterID rn, RegisterID rm) 1272 1272 { 1273 1273 ASSERT(!BadReg(rdLo)); … … 1280 1280 1281 1281 // rt == ARMRegisters::pc only allowed if last instruction in IT (if then) block. 1282 void str(RegisterID rt, RegisterID rn, ARMThumbImmediate imm)1282 ALWAYS_INLINE void str(RegisterID rt, RegisterID rn, ARMThumbImmediate imm) 1283 1283 { 1284 1284 ASSERT(rt != ARMRegisters::pc); … … 1305 1305 // MEM[index ? _tmp : _reg] = REG[rt] 1306 1306 // if (wback) REG[rn] = _tmp 1307 void str(RegisterID rt, RegisterID rn, int offset, bool index, bool wback)1307 ALWAYS_INLINE void str(RegisterID rt, RegisterID rn, int offset, bool index, bool wback) 1308 1308 { 1309 1309 ASSERT(rt != ARMRegisters::pc); … … 1328 1328 1329 1329 // rt == ARMRegisters::pc only allowed if last instruction in IT (if then) block. 1330 void str(RegisterID rt, RegisterID rn, RegisterID rm, unsigned shift=0)1330 ALWAYS_INLINE void str(RegisterID rt, RegisterID rn, RegisterID rm, unsigned shift = 0) 1331 1331 { 1332 1332 ASSERT(rn != ARMRegisters::pc); … … 1340 1340 } 1341 1341 1342 void sub(RegisterID rd, RegisterID rn, ARMThumbImmediate imm)1342 ALWAYS_INLINE void sub(RegisterID rd, RegisterID rn, ARMThumbImmediate imm) 1343 1343 { 1344 1344 // Rd can only be SP if Rn is also SP. … … 1369 1369 } 1370 1370 1371 void sub(RegisterID rd, ARMThumbImmediate imm, RegisterID rn)1371 ALWAYS_INLINE void sub(RegisterID rd, ARMThumbImmediate imm, RegisterID rn) 1372 1372 { 1373 1373 ASSERT(rd != ARMRegisters::pc); … … 1382 1382 } 1383 1383 1384 void sub(RegisterID rd, RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift)1384 ALWAYS_INLINE void sub(RegisterID rd, RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift) 1385 1385 { 1386 1386 ASSERT((rd != ARMRegisters::sp) || (rn == ARMRegisters::sp)); … … 1392 1392 1393 1393 // NOTE: In an IT block, add doesn't modify the flags register. 1394 void sub(RegisterID rd, RegisterID rn, RegisterID rm)1394 ALWAYS_INLINE void sub(RegisterID rd, RegisterID rn, RegisterID rm) 1395 1395 { 1396 1396 if (!((rd | rn | rm) & 8)) … … 1426 1426 1427 1427 // Not allowed in an IT (if then) block? 1428 void sub_S(RegisterID rd, RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift)1428 ALWAYS_INLINE void sub_S(RegisterID rd, RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift) 1429 1429 { 1430 1430 ASSERT((rd != ARMRegisters::sp) || (rn == ARMRegisters::sp)); … … 1436 1436 1437 1437 // Not allowed in an IT (if then) block. 1438 void sub_S(RegisterID rd, RegisterID rn, RegisterID rm)1438 ALWAYS_INLINE void sub_S(RegisterID rd, RegisterID rn, RegisterID rm) 1439 1439 { 1440 1440 if (!((rd | rn | rm) & 8)) … … 1444 1444 } 1445 1445 1446 void tst(RegisterID rn, ARMThumbImmediate imm)1446 ALWAYS_INLINE void tst(RegisterID rn, ARMThumbImmediate imm) 1447 1447 { 1448 1448 ASSERT(!BadReg(rn)); … … 1452 1452 } 1453 1453 1454 void tst(RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift)1454 ALWAYS_INLINE void tst(RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift) 1455 1455 { 1456 1456 ASSERT(!BadReg(rn)); … … 1459 1459 } 1460 1460 1461 void tst(RegisterID rn, RegisterID rm)1461 ALWAYS_INLINE void tst(RegisterID rn, RegisterID rm) 1462 1462 { 1463 1463 if ((rn | rm) & 8) … … 1577 1577 // Assembler admin methods: 1578 1578 1579 static bool linkRecordSourceComparator(const LinkRecord& a, const LinkRecord& b)1579 static ALWAYS_INLINE bool linkRecordSourceComparator(const LinkRecord& a, const LinkRecord& b) 1580 1580 { 1581 1581 return a.from() < b.from(); … … 1664 1664 } 1665 1665 1666 void link(LinkRecord& record, uint8_t* from, uint8_t* to)1666 void ALWAYS_INLINE link(LinkRecord& record, uint8_t* from, uint8_t* to) 1667 1667 { 1668 1668 switch (record.linkType()) { … … 2166 2166 class ARMInstructionFormatter { 2167 2167 public: 2168 void oneWordOp5Reg3Imm8(OpcodeID op, RegisterID rd, uint8_t imm)2168 ALWAYS_INLINE void oneWordOp5Reg3Imm8(OpcodeID op, RegisterID rd, uint8_t imm) 2169 2169 { 2170 2170 m_buffer.putShort(op | (rd << 8) | imm); 2171 2171 } 2172 2172 2173 void oneWordOp5Imm5Reg3Reg3(OpcodeID op, uint8_t imm, RegisterID reg1, RegisterID reg2)2173 ALWAYS_INLINE void oneWordOp5Imm5Reg3Reg3(OpcodeID op, uint8_t imm, RegisterID reg1, RegisterID reg2) 2174 2174 { 2175 2175 m_buffer.putShort(op | (imm << 6) | (reg1 << 3) | reg2); 2176 2176 } 2177 2177 2178 void oneWordOp7Reg3Reg3Reg3(OpcodeID op, RegisterID reg1, RegisterID reg2, RegisterID reg3)2178 ALWAYS_INLINE void oneWordOp7Reg3Reg3Reg3(OpcodeID op, RegisterID reg1, RegisterID reg2, RegisterID reg3) 2179 2179 { 2180 2180 m_buffer.putShort(op | (reg1 << 6) | (reg2 << 3) | reg3); 2181 2181 } 2182 2182 2183 void oneWordOp8Imm8(OpcodeID op, uint8_t imm)2183 ALWAYS_INLINE void oneWordOp8Imm8(OpcodeID op, uint8_t imm) 2184 2184 { 2185 2185 m_buffer.putShort(op | imm); 2186 2186 } 2187 2187 2188 void oneWordOp8RegReg143(OpcodeID op, RegisterID reg1, RegisterID reg2)2188 ALWAYS_INLINE void oneWordOp8RegReg143(OpcodeID op, RegisterID reg1, RegisterID reg2) 2189 2189 { 2190 2190 m_buffer.putShort(op | ((reg2 & 8) << 4) | (reg1 << 3) | (reg2 & 7)); 2191 2191 } 2192 void oneWordOp9Imm7(OpcodeID op, uint8_t imm) 2192 2193 ALWAYS_INLINE void oneWordOp9Imm7(OpcodeID op, uint8_t imm) 2193 2194 { 2194 2195 m_buffer.putShort(op | imm); 2195 2196 } 2196 2197 2197 void oneWordOp10Reg3Reg3(OpcodeID op, RegisterID reg1, RegisterID reg2)2198 ALWAYS_INLINE void oneWordOp10Reg3Reg3(OpcodeID op, RegisterID reg1, RegisterID reg2) 2198 2199 { 2199 2200 m_buffer.putShort(op | (reg1 << 3) | reg2); 2200 2201 } 2201 2202 2202 void twoWordOp12Reg4FourFours(OpcodeID1 op, RegisterID reg, FourFours ff)2203 ALWAYS_INLINE void twoWordOp12Reg4FourFours(OpcodeID1 op, RegisterID reg, FourFours ff) 2203 2204 { 2204 2205 m_buffer.putShort(op | reg); … … 2206 2207 } 2207 2208 2208 void twoWordOp16FourFours(OpcodeID1 op, FourFours ff)2209 ALWAYS_INLINE void twoWordOp16FourFours(OpcodeID1 op, FourFours ff) 2209 2210 { 2210 2211 m_buffer.putShort(op); … … 2212 2213 } 2213 2214 2214 void twoWordOp16Op16(OpcodeID1 op1, OpcodeID2 op2)2215 ALWAYS_INLINE void twoWordOp16Op16(OpcodeID1 op1, OpcodeID2 op2) 2215 2216 { 2216 2217 m_buffer.putShort(op1); … … 2218 2219 } 2219 2220 2220 void twoWordOp5i6Imm4Reg4EncodedImm(OpcodeID1 op, int imm4, RegisterID rd, ARMThumbImmediate imm)2221 ALWAYS_INLINE void twoWordOp5i6Imm4Reg4EncodedImm(OpcodeID1 op, int imm4, RegisterID rd, ARMThumbImmediate imm) 2221 2222 { 2222 2223 ARMThumbImmediate newImm = imm; … … 2227 2228 } 2228 2229 2229 void twoWordOp12Reg4Reg4Imm12(OpcodeID1 op, RegisterID reg1, RegisterID reg2, uint16_t imm)2230 ALWAYS_INLINE void twoWordOp12Reg4Reg4Imm12(OpcodeID1 op, RegisterID reg1, RegisterID reg2, uint16_t imm) 2230 2231 { 2231 2232 m_buffer.putShort(op | reg1); … … 2237 2238 // Where 1s in the pattern come from op1, 2s in the pattern come from op2, S is the provided size bit. 2238 2239 // Operands provide 5 bit values of the form Aaaaa, Bbbbb, Ccccc. 2239 void vfpOp(OpcodeID1 op1, OpcodeID2 op2, bool size, VFPOperand a, VFPOperand b, VFPOperand c)2240 ALWAYS_INLINE void vfpOp(OpcodeID1 op1, OpcodeID2 op2, bool size, VFPOperand a, VFPOperand b, VFPOperand c) 2240 2241 { 2241 2242 ASSERT(!(op1 & 0x004f)); … … 2247 2248 // Arm vfp addresses can be offset by a 9-bit ones-comp immediate, left shifted by 2. 2248 2249 // (i.e. +/-(0..255) 32-bit words) 2249 void vfpMemOp(OpcodeID1 op1, OpcodeID2 op2, bool size, RegisterID rn, VFPOperand rd, int32_t imm)2250 ALWAYS_INLINE void vfpMemOp(OpcodeID1 op1, OpcodeID2 op2, bool size, RegisterID rn, VFPOperand rd, int32_t imm) 2250 2251 { 2251 2252 bool up = true; -
trunk/Source/JavaScriptCore/assembler/LinkBuffer.h
r87612 r90426 249 249 // Copy the instructions from the last jump to the current one. 250 250 size_t regionSize = jumpsToLink[i].from() - readPtr; 251 memcpy(outData + writePtr, inData + readPtr, regionSize); 251 uint16_t* copySource = reinterpret_cast<uint16_t*>(inData + readPtr); 252 uint16_t* copyEnd = reinterpret_cast<uint16_t*>(inData + readPtr + regionSize); 253 uint16_t* copyDst = reinterpret_cast<uint16_t*>(outData + writePtr); 254 ASSERT(!(regionSize % 2)); 255 ASSERT(!(readPtr % 2)); 256 ASSERT(!(writePtr % 2)); 257 while (copySource != copyEnd) 258 *copyDst++ = *copySource++; 252 259 m_assembler->recordLinkOffsets(readPtr, jumpsToLink[i].from(), offset); 253 260 readPtr += regionSize; -
trunk/Source/JavaScriptCore/assembler/MacroAssemblerARMv7.h
r90237 r90426 1127 1127 } 1128 1128 1129 Call nearCall()1129 ALWAYS_INLINE Call nearCall() 1130 1130 { 1131 1131 moveFixedWidthEncoding(TrustedImm32(0), dataTempRegister); … … 1133 1133 } 1134 1134 1135 Call call()1135 ALWAYS_INLINE Call call() 1136 1136 { 1137 1137 moveFixedWidthEncoding(TrustedImm32(0), dataTempRegister); … … 1139 1139 } 1140 1140 1141 Call call(RegisterID target)1141 ALWAYS_INLINE Call call(RegisterID target) 1142 1142 { 1143 1143 return Call(m_assembler.blx(target), Call::None); 1144 1144 } 1145 1145 1146 Call call(Address address)1146 ALWAYS_INLINE Call call(Address address) 1147 1147 { 1148 1148 load32(address, dataTempRegister); … … 1150 1150 } 1151 1151 1152 void ret()1152 ALWAYS_INLINE void ret() 1153 1153 { 1154 1154 m_assembler.bx(linkRegister); … … 1199 1199 } 1200 1200 1201 DataLabel32 moveWithPatch(TrustedImm32 imm, RegisterID dst)1201 ALWAYS_INLINE DataLabel32 moveWithPatch(TrustedImm32 imm, RegisterID dst) 1202 1202 { 1203 1203 moveFixedWidthEncoding(imm, dst); … … 1205 1205 } 1206 1206 1207 DataLabelPtr moveWithPatch(TrustedImmPtr imm, RegisterID dst)1207 ALWAYS_INLINE DataLabelPtr moveWithPatch(TrustedImmPtr imm, RegisterID dst) 1208 1208 { 1209 1209 moveFixedWidthEncoding(TrustedImm32(imm), dst); … … 1211 1211 } 1212 1212 1213 Jump branchPtrWithPatch(RelationalCondition cond, RegisterID left, DataLabelPtr& dataLabel, TrustedImmPtr initialRightValue = TrustedImmPtr(0))1213 ALWAYS_INLINE Jump branchPtrWithPatch(RelationalCondition cond, RegisterID left, DataLabelPtr& dataLabel, TrustedImmPtr initialRightValue = TrustedImmPtr(0)) 1214 1214 { 1215 1215 dataLabel = moveWithPatch(initialRightValue, dataTempRegister); … … 1217 1217 } 1218 1218 1219 Jump branchPtrWithPatch(RelationalCondition cond, Address left, DataLabelPtr& dataLabel, TrustedImmPtr initialRightValue = TrustedImmPtr(0))1219 ALWAYS_INLINE Jump branchPtrWithPatch(RelationalCondition cond, Address left, DataLabelPtr& dataLabel, TrustedImmPtr initialRightValue = TrustedImmPtr(0)) 1220 1220 { 1221 1221 load32(left, addressTempRegister); … … 1224 1224 } 1225 1225 1226 DataLabelPtr storePtrWithPatch(TrustedImmPtr initialValue, ImplicitAddress address)1226 ALWAYS_INLINE DataLabelPtr storePtrWithPatch(TrustedImmPtr initialValue, ImplicitAddress address) 1227 1227 { 1228 1228 DataLabelPtr label = moveWithPatch(initialValue, dataTempRegister); … … 1230 1230 return label; 1231 1231 } 1232 DataLabelPtr storePtrWithPatch(ImplicitAddress address) { return storePtrWithPatch(TrustedImmPtr(0), address); }1233 1234 1235 Call tailRecursiveCall()1232 ALWAYS_INLINE DataLabelPtr storePtrWithPatch(ImplicitAddress address) { return storePtrWithPatch(TrustedImmPtr(0), address); } 1233 1234 1235 ALWAYS_INLINE Call tailRecursiveCall() 1236 1236 { 1237 1237 // Like a normal call, but don't link. … … 1240 1240 } 1241 1241 1242 Call makeTailRecursiveCall(Jump oldJump)1242 ALWAYS_INLINE Call makeTailRecursiveCall(Jump oldJump) 1243 1243 { 1244 1244 oldJump.link(this); … … 1258 1258 } 1259 1259 1260 Jump jump()1260 ALWAYS_INLINE Jump jump() 1261 1261 { 1262 1262 moveFixedWidthEncoding(TrustedImm32(0), dataTempRegister); … … 1264 1264 } 1265 1265 1266 Jump makeBranch(ARMv7Assembler::Condition cond)1266 ALWAYS_INLINE Jump makeBranch(ARMv7Assembler::Condition cond) 1267 1267 { 1268 1268 m_assembler.it(cond, true, true); … … 1270 1270 return Jump(m_assembler.bx(dataTempRegister), inUninterruptedSequence() ? ARMv7Assembler::JumpConditionFixedSize : ARMv7Assembler::JumpCondition, cond); 1271 1271 } 1272 Jump makeBranch(RelationalCondition cond) { return makeBranch(armV7Condition(cond)); }1273 Jump makeBranch(ResultCondition cond) { return makeBranch(armV7Condition(cond)); }1274 Jump makeBranch(DoubleCondition cond) { return makeBranch(armV7Condition(cond)); }1272 ALWAYS_INLINE Jump makeBranch(RelationalCondition cond) { return makeBranch(armV7Condition(cond)); } 1273 ALWAYS_INLINE Jump makeBranch(ResultCondition cond) { return makeBranch(armV7Condition(cond)); } 1274 ALWAYS_INLINE Jump makeBranch(DoubleCondition cond) { return makeBranch(armV7Condition(cond)); } 1275 1275 1276 1276 ArmAddress setupArmAddress(BaseIndex address)
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