Changeset 95684 in webkit

Timestamp:

Sep 21, 2011 4:49:24 PM (13 years ago)

Author:

barraclough@apple.com

Message:

DFG JIT should be able to compile op_throw
​https://bugs.webkit.org/show_bug.cgi?id=68571

Patch by Filip Pizlo <​fpizlo@apple.com> on 2011-09-21
Reviewed by Geoffrey Garen.

This compiles op_throw in the simplest way possible: it's an OSR
point back to the old JIT. This is a good step towards increasing
coverage, particularly on Kraken, but it's neutral because the
same functions that do throw also use some other unsupported
opcodes.

• dfg/DFGByteCodeParser.cpp:

(JSC::DFG::ByteCodeParser::parseBlock):

• dfg/DFGCapabilities.h:

(JSC::DFG::canCompileOpcode):

• dfg/DFGNode.h:
• dfg/DFGPropagator.cpp:

(JSC::DFG::Propagator::propagateNodePredictions):

• dfg/DFGSpeculativeJIT.cpp:

(JSC::DFG::SpeculativeJIT::compile):

Location:

trunk/Source/JavaScriptCore

Files:

• ChangeLog (modified) (1 diff)
• dfg/DFGGPRInfo.h (modified) (3 diffs)

trunk/Source/JavaScriptCore/ChangeLog

@@ -120 +120 @@
         (WTF::BitVector::resizeOutOfLine):
         (WTF::BitVector::bits):
+
+2011-09-21  Gavin Barraclough  <barraclough@apple.com>
+
+        Add X86 GPRInfo for DFG JIT.
+        https://bugs.webkit.org/show_bug.cgi?id=68586
+
+        Reviewed by Geoff Garen.
+
+        * dfg/DFGGPRInfo.h:
+        (JSC::DFG::GPRInfo::toRegister):
+        (JSC::DFG::GPRInfo::toIndex):
+        (JSC::DFG::GPRInfo::debugName):
 
 2011-09-21  Gavin Barraclough  <barraclough@apple.com>

trunk/Source/JavaScriptCore/dfg/DFGGPRInfo.h

@@ -37 +37 @@
 #define InvalidGPRReg ((GPRReg)-1)
 
+#if CPU(X86)
+
+class GPRInfo {
+public:
+    typedef GPRReg RegisterType;
+    static const unsigned numberOfRegisters = 4;
+
+    // These registers match the baseline JIT.
+    static const GPRReg cachedResultRegister = X86Registers::eax;
+    static const GPRReg timeoutCheckRegister = X86Registers::esi;
+    static const GPRReg callFrameRegister = X86Registers::edi;
+    // Temporary registers.
+    static const GPRReg regT0 = X86Registers::eax;
+    static const GPRReg regT1 = X86Registers::edx;
+    static const GPRReg regT2 = X86Registers::ecx;
+    static const GPRReg regT3 = X86Registers::ebx;
+    // These constants provide the names for the general purpose argument & return value registers.
+    static const GPRReg argumentGPR0 = X86Registers::ecx; // regT2
+    static const GPRReg argumentGPR1 = X86Registers::edx; // regT1
+    static const GPRReg returnValueGPR = X86Registers::eax; // regT0
+    static const GPRReg returnValueGPR2 = X86Registers::edx; // regT1
+
+    static GPRReg toRegister(unsigned index)
+    {
+        ASSERT(index < numberOfRegisters);
+        static const GPRReg registerForIndex[numberOfRegisters] = { regT0, regT1, regT2, regT3, };
+        return registerForIndex[index];
+    }
+
+    static unsigned toIndex(GPRReg reg)
+    {
+        ASSERT(reg != InvalidGPRReg);
+        ASSERT(reg < 8);
+        static const unsigned indexForRegister[8] = { 0, 2, 1, 3, InvalidIndex, InvalidIndex, InvalidIndex, InvalidIndex };
+        unsigned result = indexForRegister[reg];
+        ASSERT(result != InvalidIndex);
+        return result;
+    }
+
+#ifndef NDEBUG
+    static const char* debugName(GPRReg reg)
+    {
+        ASSERT(reg != InvalidGPRReg);
+        ASSERT(reg < 8);
+        static const char* nameForRegister[8] = {
+            "rax", "rcx", "rdx", "rbx",
+            "rsp", "rbp", "rsi", "rdi",
+        };
+        return nameForRegister[reg];
+    }
+#endif
+private:
+
+    static const unsigned InvalidIndex = 0xffffffff;
+};
+
+#endif
+
+#if CPU(X86_64)
+
 class GPRInfo {
 public:
@@ -42 +102 @@
     static const unsigned numberOfRegisters = 9;
 
-    // These registers match the old JIT.
+    // These registers match the baseline JIT.
     static const GPRReg cachedResultRegister = X86Registers::eax;
     static const GPRReg timeoutCheckRegister = X86Registers::r12;
@@ -102 +162 @@
 };
 
+#endif
+
 typedef RegisterBank<GPRInfo>::iterator gpr_iterator;