Changeset 285173 in webkit

Timestamp:

Nov 2, 2021, 12:26:52 PM (5 years ago)

Author:

Ross Kirsling

Message:

[JSC][LLInt] Reverse unintended effects of r285152
​https://bugs.webkit.org/show_bug.cgi?id=232633

Reviewed by Saam Barati.

The previous patch was not intended to change the generated assembly whatsoever,
but it turns out that 3-argument syntax produces, e.g. vsub instead of sub on x86.

As such, this patch does away with the 3-arg cases and merely clarifies names as rhs, lhs across the board.

(Also: Fix a line from the previous patch where a macro was not referring to a passed label properly.)

• llint/LowLevelInterpreter32_64.asm:
• llint/LowLevelInterpreter64.asm:

Location:

trunk/Source/JavaScriptCore

Files:

• ChangeLog (modified) (1 diff)
• llint/LowLevelInterpreter32_64.asm (modified) (5 diffs)
• llint/LowLevelInterpreter64.asm (modified) (6 diffs)

trunk/Source/JavaScriptCore/ChangeLog

@@ +1 @@
+2021-11-02  Ross Kirsling  <ross.kirsling@sony.com>
+
+        [JSC][LLInt] Reverse unintended effects of r285152
+        https://bugs.webkit.org/show_bug.cgi?id=232633
+
+        Reviewed by Saam Barati.
+
+        The previous patch was not intended to change the generated assembly whatsoever,
+        but it turns out that 3-argument syntax produces, e.g. `vsub` instead of `sub` on x86.
+
+        As such, this patch does away with the 3-arg cases and merely clarifies names as `rhs, lhs` across the board.
+
+        (Also: Fix a line from the previous patch where a macro was not referring to a passed label properly.)
+
+        * llint/LowLevelInterpreter32_64.asm:
+        * llint/LowLevelInterpreter64.asm:
+
 2021-11-02  Saam Barati  <sbarati@apple.com>
 

trunk/Source/JavaScriptCore/llint/LowLevelInterpreter32_64.asm

@@ -1136 +1136 @@
         get(m_dst, t1)
         fii2d t0, t2, ft0
-        doubleOperation(ft0, ft1, ft0)
+        doubleOperation(ft0, ft1)
         stored ft0, [cfr, t1, 8]
         dispatch()
@@ -1147 +1147 @@
         ci2ds t0, ft0
         fii2d t1, t3, ft1
-        doubleOperation(ft0, ft1, ft0)
+        doubleOperation(ft0, ft1)
         stored ft0, [cfr, t2, 8]
         dispatch()
@@ -1169 +1169 @@
 binaryOp(add, OpAdd,
     macro (lhs, rhs, slow) baddio rhs, lhs, slow end,
-    macro (left, right, result) addd left, right, result end)
+    macro (lhs, rhs) addd rhs, lhs end)
 
 
@@ -1184 +1184 @@
         storei scratch, PayloadOffset[cfr, index, 8]
     end,
-    macro (left, right, result) muld left, right, result end)
+    macro (lhs, rhs) muld rhs, lhs end)
 
 
 binaryOp(sub, OpSub,
     macro (lhs, rhs, slow) bsubio rhs, lhs, slow end,
-    macro (left, right, result) subd left, right, result end)
+    macro (lhs, rhs) subd rhs, lhs end)
 
 
@@ -1205 +1205 @@
     .done:
     end,
-    macro (left, right, result) divd left, right, result end)
+    macro (lhs, rhs) divd rhs, lhs end)
 
 

trunk/Source/JavaScriptCore/llint/LowLevelInterpreter64.asm

@@ -1200 +1200 @@
         addq numberTag, t0
         fq2d t0, ft0
-        doubleOperation(ft0, ft1, ft0)
+        doubleOperation(ft0, ft1)
         fd2q ft0, t0
         subq numberTag, t0
@@ -1214 +1214 @@
         addq numberTag, t1
         fq2d t1, ft1
-        doubleOperation(ft0, ft1, ft0)
+        doubleOperation(ft0, ft1)
         fd2q ft0, t0
         subq numberTag, t0
@@ -1232 +1232 @@
             btiz rhs, slow
             bineq rhs, -1, .notNeg2TwoThe31DivByNeg1
-            bieq lhs, -2147483648, .slow
+            bieq lhs, -2147483648, slow
         .notNeg2TwoThe31DivByNeg1:
             btinz lhs, .intOK
@@ -1245 +1245 @@
             storeq t0, [cfr, index, 8]
         end,
-        macro (left, right, result) divd left, right, result end)
+        macro (lhs, rhs) divd rhs, lhs end)
 else
     slowPathOp(div)
@@ -1263 +1263 @@
         storeq t3, [cfr, index, 8]
     end,
-    macro (left, right, result) muld left, right, result end)
+    macro (lhs, rhs) muld rhs, lhs end)
 
 
@@ -1278 +1278 @@
 binaryOp(add, OpAdd,
     macro (lhs, rhs, slow) baddio rhs, lhs, slow end,
-    macro (left, right, result) addd left, right, result end)
+    macro (lhs, rhs) addd rhs, lhs end)
 
 
 binaryOp(sub, OpSub,
     macro (lhs, rhs, slow) bsubio rhs, lhs, slow end,
-    macro (left, right, result) subd left, right, result end)
+    macro (lhs, rhs) subd rhs, lhs end)