Changeset 154016 in webkit
- Timestamp:
- Aug 13, 2013 11:59:14 AM (11 years ago)
- Location:
- trunk/Source/JavaScriptCore
- Files:
-
- 7 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/Source/JavaScriptCore/ChangeLog
r154011 r154016 1 2013-08-13 Julien Brianceau <jbrianceau@nds.com> 2 3 [sh4] Prepare baseline JIT for DFG_JIT implementation. 4 https://bugs.webkit.org/show_bug.cgi?id=119758 5 6 Reviewed by Oliver Hunt. 7 8 * assembler/MacroAssemblerSH4.h: 9 - Introduce a loadEffectiveAddress function to avoid code duplication. 10 - Add ASSERTs and clean code. 11 * assembler/SH4Assembler.h: 12 - Prepare DFG_JIT implementation. 13 - Add ASSERTs. 14 * jit/JITStubs.cpp: 15 - Add SH4 specific call for assertions. 16 * jit/JITStubs.h: 17 - Cosmetic change. 18 * jit/JITStubsSH4.h: 19 - Use constants to be more flexible with sh4 JIT stack frame. 20 * jit/JSInterfaceJIT.h: 21 - Cosmetic change. 22 1 23 2013-08-13 Oliver Hunt <oliver@apple.com> 2 24 -
trunk/Source/JavaScriptCore/assembler/MacroAssemblerSH4.h
r153324 r154016 42 42 43 43 static const Scale ScalePtr = TimesFour; 44 static const FPRegisterID fscratch = SH4Registers:: fr10;44 static const FPRegisterID fscratch = SH4Registers::dr10; 45 45 static const RegisterID stackPointerRegister = SH4Registers::sp; 46 46 static const RegisterID linkRegister = SH4Registers::pr; … … 51 51 static bool isCompactPtrAlignedAddressOffset(ptrdiff_t value) 52 52 { 53 return (value >= 0) && (value <= MaximumCompactPtrAlignedAddressOffset) ;53 return (value >= 0) && (value <= MaximumCompactPtrAlignedAddressOffset) && (!(value & 3)); 54 54 } 55 55 … … 127 127 void add32(TrustedImm32 imm, RegisterID src, RegisterID dest) 128 128 { 129 if (src != dest) 130 m_assembler.movlRegReg(src, dest); 129 move(src, dest); 131 130 add32(imm, dest); 132 131 } … … 167 166 void and32(TrustedImm32 imm, RegisterID dest) 168 167 { 168 if (!imm.m_value) { 169 m_assembler.movImm8(0, dest); 170 return; 171 } 172 169 173 if ((imm.m_value <= 255) && (imm.m_value >= 0) && (dest == SH4Registers::r0)) { 170 174 m_assembler.andlImm8r(imm.m_value, dest); … … 217 221 void lshift32(RegisterID src, TrustedImm32 shiftamount, RegisterID dest) 218 222 { 219 if (src != dest) 220 move(src, dest); 221 223 move(src, dest); 222 224 lshift32(shiftamount, dest); 223 225 } … … 231 233 void mul32(TrustedImm32 imm, RegisterID src, RegisterID dest) 232 234 { 233 RegisterID scr = claimScratch(); 234 move(imm, scr); 235 if (src != dest) 236 move(src, dest); 237 mul32(scr, dest); 238 releaseScratch(scr); 235 if (src == dest) { 236 RegisterID immval = claimScratch(); 237 move(imm, immval); 238 mul32(immval, dest); 239 releaseScratch(immval); 240 } else { 241 move(imm, dest); 242 mul32(src, dest); 243 } 239 244 } 240 245 … … 320 325 void rshift32(RegisterID src, TrustedImm32 imm, RegisterID dest) 321 326 { 322 if (src != dest) 323 move(src, dest); 327 move(src, dest); 324 328 rshift32(imm, dest); 325 329 } … … 338 342 RegisterID scratchReg = claimScratch(); 339 343 340 m _assembler.loadConstant(reinterpret_cast<uint32_t>(address.m_ptr), scratchReg);344 move(TrustedImmPtr(address.m_ptr), scratchReg); 341 345 m_assembler.movlMemReg(scratchReg, result); 342 346 … … 361 365 RegisterID scratchReg = claimScratch(); 362 366 363 m _assembler.loadConstant(reinterpret_cast<uint32_t>(address.m_ptr), scratchReg);367 move(TrustedImmPtr(address.m_ptr), scratchReg); 364 368 m_assembler.movlMemReg(scratchReg, result); 365 369 … … 382 386 383 387 // Add 32-bit LSB first. 384 m _assembler.loadConstant(reinterpret_cast<uint32_t>(address.m_ptr), scr1);385 m_assembler.movlMemReg(scr 1, scr1); // scr1 = 32-bit LSB of int64 @ address388 move(TrustedImmPtr(address.m_ptr), scratchReg3); 389 m_assembler.movlMemReg(scratchReg3, scr1); // scr1 = 32-bit LSB of int64 @ address 386 390 m_assembler.loadConstant(imm.m_value, scr2); 387 391 m_assembler.clrt(); 388 392 m_assembler.addclRegReg(scr1, scr2); 389 m_assembler.loadConstant(reinterpret_cast<uint32_t>(address.m_ptr), scr1); 390 m_assembler.movlRegMem(scr2, scr1); // Update address with 32-bit LSB result. 393 m_assembler.movlRegMem(scr2, scratchReg3); // Update address with 32-bit LSB result. 391 394 392 395 // Then add 32-bit MSB. 393 m_assembler.addlImm8r(4, scr 1);394 m_assembler.movlMemReg(scr 1, scr1); // scr1 = 32-bit MSB of int64 @ address396 m_assembler.addlImm8r(4, scratchReg3); 397 m_assembler.movlMemReg(scratchReg3, scr1); // scr1 = 32-bit MSB of int64 @ address 395 398 m_assembler.movt(scr2); 396 399 if (imm.m_value < 0) 397 400 m_assembler.addlImm8r(-1, scr2); // Sign extend imm value if needed. 398 401 m_assembler.addvlRegReg(scr2, scr1); 399 m_assembler.loadConstant(reinterpret_cast<uint32_t>(address.m_ptr) + 4, scr2); 400 m_assembler.movlRegMem(scr1, scr2); // Update (address + 4) with 32-bit MSB result. 402 m_assembler.movlRegMem(scr1, scratchReg3); // Update (address + 4) with 32-bit MSB result. 401 403 402 404 releaseScratch(scr2); … … 455 457 if (((cond == Equal) || (cond == NotEqual)) && (dst == SH4Registers::r0) && m_assembler.isImmediate(imm)) { 456 458 m_assembler.cmpEqImmR0(imm, dst); 459 return; 460 } 461 462 if (((cond == Equal) || (cond == NotEqual)) && !imm) { 463 m_assembler.testlRegReg(dst, dst); 457 464 return; 458 465 } … … 491 498 { 492 499 RegisterID scr = claimScratch(); 500 load32(base, offset, scr); 501 493 502 RegisterID scr1 = claimScratch(); 494 495 if ((offset < 0) || (offset >= 64)) { 496 m_assembler.loadConstant(offset, scr); 497 m_assembler.addlRegReg(base, scr); 498 m_assembler.movlMemReg(scr, scr); 499 } else if (offset) 500 m_assembler.movlMemReg(offset >> 2, base, scr); 501 else 502 m_assembler.movlMemReg(base, scr); 503 if (m_assembler.isImmediate(imm)) 504 m_assembler.movImm8(imm, scr1); 505 else 506 m_assembler.loadConstant(imm, scr1); 503 move(TrustedImm32(imm), scr1); 507 504 508 505 m_assembler.testlRegReg(scr, scr1); … … 552 549 void compare32(int imm, int offset, RegisterID base, RelationalCondition cond) 553 550 { 554 if (!offset) { 555 RegisterID scr = claimScratch(); 556 RegisterID scr1 = claimScratch(); 557 m_assembler.movlMemReg(base, scr); 558 m_assembler.loadConstant(imm, scr1); 559 m_assembler.cmplRegReg(scr1, scr, SH4Condition(cond)); 560 releaseScratch(scr1); 561 releaseScratch(scr); 562 return; 563 } 564 565 if ((offset < 0) || (offset >= 64)) { 566 RegisterID scr = claimScratch(); 567 RegisterID scr1 = claimScratch(); 568 m_assembler.loadConstant(offset, scr); 569 m_assembler.addlRegReg(base, scr); 570 m_assembler.movlMemReg(scr, scr); 571 m_assembler.loadConstant(imm, scr1); 572 m_assembler.cmplRegReg(scr1, scr, SH4Condition(cond)); 573 releaseScratch(scr1); 574 releaseScratch(scr); 575 return; 576 } 577 578 RegisterID scr = claimScratch(); 551 RegisterID scr = claimScratch(); 552 load32(base, offset, scr); 553 579 554 RegisterID scr1 = claimScratch(); 580 m _assembler.movlMemReg(offset >> 2, base, scr);581 m_assembler.loadConstant(imm, scr1); 555 move(TrustedImm32(imm), scr1); 556 582 557 m_assembler.cmplRegReg(scr1, scr, SH4Condition(cond)); 558 583 559 releaseScratch(scr1); 584 560 releaseScratch(scr); … … 586 562 587 563 // Memory access operation 564 565 ALWAYS_INLINE void loadEffectiveAddress(BaseIndex address, RegisterID dest, int extraoffset = 0) 566 { 567 if (dest == address.base) { 568 RegisterID scaledIndex = claimScratch(); 569 move(address.index, scaledIndex); 570 lshift32(TrustedImm32(address.scale), scaledIndex); 571 add32(scaledIndex, dest); 572 releaseScratch(scaledIndex); 573 } else { 574 move(address.index, dest); 575 lshift32(TrustedImm32(address.scale), dest); 576 add32(address.base, dest); 577 } 578 579 add32(TrustedImm32(address.offset + extraoffset), dest); 580 } 588 581 589 582 void load32(ImplicitAddress address, RegisterID dest) … … 635 628 void load32(const void* address, RegisterID dest) 636 629 { 637 m _assembler.loadConstant(reinterpret_cast<uint32_t>(const_cast<void*>(address)), dest);630 move(TrustedImmPtr(address), dest); 638 631 m_assembler.movlMemReg(dest, dest); 639 632 } … … 734 727 { 735 728 RegisterID scr = claimScratch(); 729 730 loadEffectiveAddress(address, scr); 731 736 732 RegisterID scr1 = claimScratch(); 737 738 move(address.index, scr);739 lshift32(TrustedImm32(address.scale), scr);740 741 if (address.offset)742 add32(TrustedImm32(address.offset), scr);743 744 add32(address.base, scr);745 733 load8PostInc(scr, scr1); 746 734 load8(scr, dest); … … 781 769 move(address.index, scr); 782 770 lshift32(TrustedImm32(address.scale), scr); 783 784 if (address.offset) 785 add32(TrustedImm32(address.offset), scr); 771 add32(TrustedImm32(address.offset), scr); 786 772 787 773 if (address.base == SH4Registers::r0) … … 815 801 void store8(TrustedImm32 imm, void* address) 816 802 { 803 ASSERT((imm.m_value >= -128) && (imm.m_value <= 127)); 804 RegisterID dstptr = claimScratch(); 805 move(TrustedImmPtr(address), dstptr); 817 806 RegisterID srcval = claimScratch(); 818 RegisterID dstptr = claimScratch();819 807 move(imm, srcval); 820 m_assembler.loadConstant(reinterpret_cast<uint32_t>(address), dstptr);821 808 m_assembler.movbRegMem(srcval, dstptr); 822 809 releaseScratch(dstptr); … … 895 882 RegisterID scr1 = claimScratch(); 896 883 m_assembler.loadConstant(imm.m_value, scr); 897 m _assembler.loadConstant(reinterpret_cast<uint32_t>(address), scr1);884 move(TrustedImmPtr(address), scr1); 898 885 m_assembler.movlRegMem(scr, scr1); 899 886 releaseScratch(scr); … … 904 891 { 905 892 RegisterID scr = claimScratch(); 906 m _assembler.loadConstant(reinterpret_cast<uint32_t>(address), scr);893 move(TrustedImmPtr(address), scr); 907 894 m_assembler.movlRegMem(src, scr); 908 895 releaseScratch(scr); … … 934 921 { 935 922 DataLabelCompact dataLabel(this); 936 ASSERT(address.offset <= MaximumCompactPtrAlignedAddressOffset); 937 ASSERT(address.offset >= 0); 923 ASSERT(isCompactPtrAlignedAddressOffset(address.offset)); 938 924 m_assembler.movlMemRegCompact(address.offset >> 2, address.base, dest); 939 925 return dataLabel; … … 968 954 } 969 955 970 void moveIntsToDouble(RegisterID src1, RegisterID src2, FPRegisterID dest, FPRegisterID scratch) 971 { 972 UNUSED_PARAM(scratch); 956 void moveIntsToDouble(RegisterID src1, RegisterID src2, FPRegisterID dest, FPRegisterID) 957 { 973 958 m_assembler.ldsrmfpul(src1); 974 959 m_assembler.fstsfpul((FPRegisterID)(dest + 1)); … … 989 974 RegisterID scr = claimScratch(); 990 975 991 move(address.index, scr); 992 lshift32(TrustedImm32(address.scale), scr); 993 add32(address.base, scr); 994 if (address.offset) 995 add32(TrustedImm32(address.offset), scr); 976 loadEffectiveAddress(address, scr); 996 977 997 978 m_assembler.fmovsReadrm(scr, dest); … … 1003 984 RegisterID scr = claimScratch(); 1004 985 1005 move(address.index, scr); 1006 lshift32(TrustedImm32(address.scale), scr); 1007 add32(address.base, scr); 1008 if (address.offset) 1009 add32(TrustedImm32(address.offset), scr); 986 loadEffectiveAddress(address, scr); 1010 987 1011 988 m_assembler.fmovsReadrminc(scr, (FPRegisterID)(dest + 1)); … … 1036 1013 { 1037 1014 RegisterID scr = claimScratch(); 1038 m _assembler.loadConstant(reinterpret_cast<uint32_t>(address), scr);1015 move(TrustedImmPtr(address), scr); 1039 1016 m_assembler.fmovsReadrminc(scr, (FPRegisterID)(dest + 1)); 1040 1017 m_assembler.fmovsReadrm(scr, dest); … … 1045 1022 { 1046 1023 RegisterID scr = claimScratch(); 1047 1048 move(address.index, scr); 1049 lshift32(TrustedImm32(address.scale), scr); 1050 add32(address.base, scr); 1051 if (address.offset) 1052 add32(TrustedImm32(address.offset), scr); 1053 1024 loadEffectiveAddress(address, scr); 1054 1025 m_assembler.fmovsWriterm(src, scr); 1055 1056 1026 releaseScratch(scr); 1057 1027 } … … 1071 1041 RegisterID scr = claimScratch(); 1072 1042 1073 move(address.index, scr); 1074 lshift32(TrustedImm32(address.scale), scr); 1075 add32(address.base, scr); 1076 add32(TrustedImm32(address.offset + 8), scr); 1043 loadEffectiveAddress(address, scr, 8); 1077 1044 1078 1045 m_assembler.fmovsWriterndec(src, scr); … … 1180 1147 move(SH4Registers::r0, scr1); 1181 1148 1182 move(address.index, scr); 1183 lshift32(TrustedImm32(address.scale), scr); 1184 add32(address.base, scr); 1185 1186 if (address.offset) 1187 add32(TrustedImm32(address.offset), scr); 1149 loadEffectiveAddress(address, scr); 1188 1150 1189 1151 m_assembler.ensureSpace(m_assembler.maxInstructionSize + 58, sizeof(uint32_t)); … … 1431 1393 void signExtend32ToPtr(RegisterID src, RegisterID dest) 1432 1394 { 1433 if (src != dest) 1434 move(src, dest); 1395 move(src, dest); 1435 1396 } 1436 1397 … … 1455 1416 Jump branchTruncateDoubleToInt32(FPRegisterID src, RegisterID dest, BranchTruncateType branchType = BranchIfTruncateFailed) 1456 1417 { 1418 Jump result; 1419 truncateDoubleToInt32(src, dest); 1420 RegisterID intscr = claimScratch(); 1421 m_assembler.loadConstant(0x7fffffff, intscr); 1422 m_assembler.cmplRegReg(dest, intscr, SH4Condition(Equal)); 1423 m_assembler.ensureSpace(m_assembler.maxInstructionSize + 12, sizeof(uint32_t)); 1424 if (branchType == BranchIfTruncateFailed) { 1425 m_assembler.branch(BT_OPCODE, 2); 1426 m_assembler.addlImm8r(1, intscr); 1427 m_assembler.cmplRegReg(dest, intscr, SH4Condition(Equal)); 1428 result = branchTrue(); 1429 } else { 1430 Jump out = Jump(m_assembler.je(), SH4Assembler::JumpNear); 1431 m_assembler.addlImm8r(1, intscr); 1432 m_assembler.cmplRegReg(dest, intscr, SH4Condition(Equal)); 1433 result = branchFalse(); 1434 out.link(this); 1435 } 1436 releaseScratch(intscr); 1437 return result; 1438 } 1439 1440 void truncateDoubleToInt32(FPRegisterID src, RegisterID dest) 1441 { 1457 1442 m_assembler.ftrcdrmfpul(src); 1458 1443 m_assembler.stsfpulReg(dest); 1459 m_assembler.loadConstant(0x7fffffff, scratchReg3);1460 m_assembler.cmplRegReg(dest, scratchReg3, SH4Condition(Equal));1461 m_assembler.ensureSpace(m_assembler.maxInstructionSize + 14, sizeof(uint32_t));1462 m_assembler.branch(BT_OPCODE, 2);1463 m_assembler.addlImm8r(1, scratchReg3);1464 m_assembler.cmplRegReg(dest, scratchReg3, SH4Condition(Equal));1465 return (branchType == BranchIfTruncateFailed) ? branchTrue() : branchFalse();1466 1444 } 1467 1445 … … 1634 1612 RegisterID addressTempRegister = claimScratch(); 1635 1613 1636 m _assembler.loadConstant(reinterpret_cast<uint32_t>(left.m_ptr), addressTempRegister);1614 move(TrustedImmPtr(left.m_ptr), addressTempRegister); 1637 1615 m_assembler.movlMemReg(addressTempRegister, addressTempRegister); 1638 1616 compare32(right.m_value, addressTempRegister, cond); … … 1647 1625 { 1648 1626 ASSERT(!(right.m_value & 0xFFFFFF00)); 1649 RegisterID scr = claimScratch(); 1650 1651 move(left.index, scr); 1652 lshift32(TrustedImm32(left.scale), scr); 1653 1654 if (left.offset) 1655 add32(TrustedImm32(left.offset), scr); 1656 add32(left.base, scr); 1657 load8(scr, scr); 1658 RegisterID scr1 = claimScratch(); 1659 m_assembler.loadConstant(right.m_value, scr1); 1660 releaseScratch(scr); 1661 releaseScratch(scr1); 1662 1663 return branch32(cond, scr, scr1); 1627 RegisterID lefttmp = claimScratch(); 1628 1629 loadEffectiveAddress(left, lefttmp); 1630 1631 load8(lefttmp, lefttmp); 1632 RegisterID righttmp = claimScratch(); 1633 m_assembler.loadConstant(right.m_value, righttmp); 1634 1635 Jump result = branch32(cond, lefttmp, righttmp); 1636 releaseScratch(lefttmp); 1637 releaseScratch(righttmp); 1638 return result; 1664 1639 } 1665 1640 … … 1705 1680 Jump branchTest32(ResultCondition cond, BaseIndex address, TrustedImm32 mask = TrustedImm32(-1)) 1706 1681 { 1682 ASSERT((cond == Zero) || (cond == NonZero)); 1683 1707 1684 RegisterID scr = claimScratch(); 1708 1685 … … 1737 1714 { 1738 1715 RegisterID scr = claimScratch(); 1739 1740 if ((address.offset < 0) || (address.offset >= 64)) { 1741 m_assembler.loadConstant(address.offset, scr); 1742 m_assembler.addlRegReg(address.base, scr); 1743 m_assembler.movlMemReg(scr, scr); 1744 } else if (address.offset) 1745 m_assembler.movlMemReg(address.offset >> 2, address.base, scr); 1746 else 1747 m_assembler.movlMemReg(address.base, scr); 1716 load32(address, scr); 1748 1717 m_assembler.jmpReg(scr); 1749 1750 1718 releaseScratch(scr); 1751 1719 } … … 1762 1730 } 1763 1731 1764 if (cond == Signed) {1765 m_assembler.addlRegReg(src, dest); 1766 // Check if dest is negative1732 m_assembler.addlRegReg(src, dest); 1733 1734 if ((cond == Signed) || (cond == PositiveOrZero)) { 1767 1735 m_assembler.cmppz(dest); 1768 return branchFalse(); 1769 } 1770 1771 if (cond == PositiveOrZero) { 1772 m_assembler.addlRegReg(src, dest); 1773 m_assembler.cmppz(dest); 1774 return branchTrue(); 1775 } 1776 1777 m_assembler.addlRegReg(src, dest); 1736 return (cond == Signed) ? branchFalse() : branchTrue(); 1737 } 1738 1778 1739 compare32(0, dest, Equal); 1779 1780 if (cond == NonZero) // NotEqual 1781 return branchFalse(); 1782 return branchTrue(); 1740 return (cond == NonZero) ? branchFalse() : branchTrue(); 1783 1741 } 1784 1742 … … 1787 1745 ASSERT((cond == Overflow) || (cond == Signed) || (cond == PositiveOrZero) || (cond == Zero) || (cond == NonZero)); 1788 1746 1789 move(imm, scratchReg3); 1790 return branchAdd32(cond, scratchReg3, dest); 1747 RegisterID immval = claimScratch(); 1748 move(imm, immval); 1749 Jump result = branchAdd32(cond, immval, dest); 1750 releaseScratch(immval); 1751 return result; 1791 1752 } 1792 1753 … … 1795 1756 ASSERT((cond == Overflow) || (cond == Signed) || (cond == PositiveOrZero) || (cond == Zero) || (cond == NonZero)); 1796 1757 1797 if (src != dest) 1798 move(src, dest); 1758 move(src, dest); 1799 1759 1800 1760 if (cond == Overflow) { … … 1806 1766 add32(imm, dest); 1807 1767 1808 if ( cond == Signed) {1768 if ((cond == Signed) || (cond == PositiveOrZero)) { 1809 1769 m_assembler.cmppz(dest); 1810 return branchFalse(); 1811 } 1812 1813 if (cond == PositiveOrZero) { 1814 m_assembler.cmppz(dest); 1815 return branchTrue(); 1770 return (cond == Signed) ? branchFalse() : branchTrue(); 1816 1771 } 1817 1772 1818 1773 compare32(0, dest, Equal); 1819 1820 if (cond == NonZero) // NotEqual 1821 return branchFalse(); 1822 return branchTrue(); 1774 return (cond == NonZero) ? branchFalse() : branchTrue(); 1823 1775 } 1824 1776 … … 1831 1783 RegisterID destptr = claimScratch(); 1832 1784 RegisterID destval = claimScratch(); 1833 m _assembler.loadConstant(reinterpret_cast<uint32_t>(dest.m_ptr), destptr);1785 move(TrustedImmPtr(dest.m_ptr), destptr); 1834 1786 m_assembler.movlMemReg(destptr, destval); 1835 1787 if (cond == Overflow) { … … 1838 1790 } else { 1839 1791 m_assembler.addlRegReg(scratchReg3, destval); 1840 if ( cond == Signed) {1792 if ((cond == Signed) || (cond == PositiveOrZero)) { 1841 1793 m_assembler.cmppz(destval); 1842 result = false; 1843 } else if (cond == PositiveOrZero) { 1844 m_assembler.cmppz(destval); 1845 result = true; 1794 result = (cond == PositiveOrZero); 1846 1795 } else { 1847 m_assembler.movImm8(0, scratchReg3); 1848 m_assembler.cmplRegReg(scratchReg3, destval, SH4Condition(cond)); 1849 result = (cond == Zero); 1796 m_assembler.testlRegReg(destval, destval); 1797 result = (cond != NonZero); 1850 1798 } 1851 1799 } … … 1875 1823 } 1876 1824 1877 m _assembler.imullRegReg(src, dest);1878 m_assembler.stsmacl(dest); 1825 mul32(src, dest); 1826 1879 1827 if (cond == Signed) { 1880 // Check if dest is negative1881 1828 m_assembler.cmppz(dest); 1882 1829 return branchFalse(); … … 1884 1831 1885 1832 compare32(0, dest, static_cast<RelationalCondition>(cond)); 1886 1887 if (cond == NonZero) // NotEqual 1888 return branchFalse(); 1889 return branchTrue(); 1833 return (cond == NonZero) ? branchFalse() : branchTrue(); 1890 1834 } 1891 1835 … … 1894 1838 ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero)); 1895 1839 1896 move(imm, scratchReg3); 1897 if (src != dest) 1898 move(src, dest); 1899 1900 return branchMul32(cond, scratchReg3, dest); 1840 if (src == dest) { 1841 move(imm, scratchReg3); 1842 return branchMul32(cond, scratchReg3, dest); 1843 } 1844 1845 move(imm, dest); 1846 return branchMul32(cond, src, dest); 1901 1847 } 1902 1848 … … 1910 1856 } 1911 1857 1858 sub32(src, dest); 1859 1912 1860 if (cond == Signed) { 1913 // Check if dest is negative 1914 m_assembler.sublRegReg(src, dest); 1915 compare32(0, dest, LessThan); 1861 m_assembler.cmppz(dest); 1862 return branchFalse(); 1863 } 1864 1865 compare32(0, dest, static_cast<RelationalCondition>(cond)); 1866 return (cond == NonZero) ? branchFalse() : branchTrue(); 1867 } 1868 1869 Jump branchSub32(ResultCondition cond, TrustedImm32 imm, RegisterID dest) 1870 { 1871 ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero)); 1872 1873 RegisterID immval = claimScratch(); 1874 move(imm, immval); 1875 Jump result = branchSub32(cond, immval, dest); 1876 releaseScratch(immval); 1877 return result; 1878 } 1879 1880 Jump branchSub32(ResultCondition cond, RegisterID src, TrustedImm32 imm, RegisterID dest) 1881 { 1882 ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero)); 1883 1884 move(src, dest); 1885 return branchSub32(cond, imm, dest); 1886 } 1887 1888 Jump branchSub32(ResultCondition cond, RegisterID src1, RegisterID src2, RegisterID dest) 1889 { 1890 ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero)); 1891 1892 if (src2 != dest) { 1893 move(src1, dest); 1894 return branchSub32(cond, src2, dest); 1895 } 1896 1897 if (cond == Overflow) { 1898 RegisterID tmpval = claimScratch(); 1899 move(src1, tmpval); 1900 m_assembler.subvlRegReg(src2, tmpval); 1901 move(tmpval, dest); 1902 releaseScratch(tmpval); 1916 1903 return branchTrue(); 1917 1904 } 1918 1905 1919 sub32(src, dest); 1906 RegisterID tmpval = claimScratch(); 1907 move(src1, tmpval); 1908 sub32(src2, tmpval); 1909 move(tmpval, dest); 1910 releaseScratch(tmpval); 1911 1912 if (cond == Signed) { 1913 m_assembler.cmppz(dest); 1914 return branchFalse(); 1915 } 1916 1920 1917 compare32(0, dest, static_cast<RelationalCondition>(cond)); 1921 1922 if (cond == NonZero) // NotEqual 1918 return (cond == NonZero) ? branchFalse() : branchTrue(); 1919 } 1920 1921 Jump branchOr32(ResultCondition cond, RegisterID src, RegisterID dest) 1922 { 1923 ASSERT((cond == Signed) || (cond == Zero) || (cond == NonZero)); 1924 1925 or32(src, dest); 1926 1927 if (cond == Signed) { 1928 m_assembler.cmppz(dest); 1923 1929 return branchFalse(); 1924 return branchTrue(); 1925 } 1926 1927 Jump branchSub32(ResultCondition cond, TrustedImm32 imm, RegisterID dest) 1928 { 1929 ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero)); 1930 1931 move(imm, scratchReg3); 1932 return branchSub32(cond, scratchReg3, dest); 1933 } 1934 1935 Jump branchSub32(ResultCondition cond, RegisterID src, TrustedImm32 imm, RegisterID dest) 1936 { 1937 move(imm, scratchReg3); 1938 if (src != dest) 1939 move(src, dest); 1940 return branchSub32(cond, scratchReg3, dest); 1941 } 1942 1943 Jump branchSub32(ResultCondition cond, RegisterID src1, RegisterID src2, RegisterID dest) 1944 { 1945 if (src1 != dest) 1946 move(src1, dest); 1947 return branchSub32(cond, src2, dest); 1948 } 1949 1950 Jump branchOr32(ResultCondition cond, RegisterID src, RegisterID dest) 1951 { 1952 ASSERT((cond == Signed) || (cond == Zero) || (cond == NonZero)); 1953 1954 if (cond == Signed) { 1955 or32(src, dest); 1956 compare32(0, dest, static_cast<RelationalCondition>(LessThan)); 1957 return branchTrue(); 1958 } 1959 1960 or32(src, dest); 1930 } 1931 1961 1932 compare32(0, dest, static_cast<RelationalCondition>(cond)); 1962 1963 if (cond == NonZero) // NotEqual 1964 return branchFalse(); 1965 return branchTrue(); 1966 } 1967 1968 void branchConvertDoubleToInt32(FPRegisterID src, RegisterID dest, JumpList& failureCases, FPRegisterID fpTemp, bool negZeroCheck = true) 1969 { 1970 m_assembler.ftrcdrmfpul(src); 1971 m_assembler.stsfpulReg(dest); 1933 return (cond == NonZero) ? branchFalse() : branchTrue(); 1934 } 1935 1936 void branchConvertDoubleToInt32(FPRegisterID src, RegisterID dest, JumpList& failureCases, FPRegisterID, bool negZeroCheck = true) 1937 { 1938 truncateDoubleToInt32(src, dest); 1972 1939 convertInt32ToDouble(dest, fscratch); 1973 1940 failureCases.append(branchDouble(DoubleNotEqualOrUnordered, fscratch, src)); 1974 1941 1975 if (negZeroCheck) { 1976 if (dest == SH4Registers::r0) 1977 m_assembler.cmpEqImmR0(0, dest); 1978 else { 1979 m_assembler.movImm8(0, scratchReg3); 1980 m_assembler.cmplRegReg(scratchReg3, dest, SH4Condition(Equal)); 1981 } 1982 failureCases.append(branchTrue()); 1983 } 1942 if (negZeroCheck) 1943 failureCases.append(branch32(Equal, dest, TrustedImm32(0))); 1984 1944 } 1985 1945 … … 2018 1978 void urshift32(RegisterID src, TrustedImm32 shiftamount, RegisterID dest) 2019 1979 { 2020 if (src != dest) 2021 move(src, dest); 2022 1980 move(src, dest); 2023 1981 urshift32(shiftamount, dest); 2024 1982 } … … 2049 2007 void breakpoint() 2050 2008 { 2009 m_assembler.ensureSpace(m_assembler.maxInstructionSize + 2); 2051 2010 m_assembler.bkpt(); 2052 2011 m_assembler.nop(); … … 2150 2109 } 2151 2110 2152 static void revertJumpReplacementToBranchPtrWithPatch(CodeLocationLabel instructionStart, RegisterID , void* initialValue)2153 { 2154 SH4Assembler::revertJump (instructionStart.dataLocation(), initialValue);2111 static void revertJumpReplacementToBranchPtrWithPatch(CodeLocationLabel instructionStart, RegisterID rd, void* initialValue) 2112 { 2113 SH4Assembler::revertJumpToMove(instructionStart.dataLocation(), rd, reinterpret_cast<int>(initialValue)); 2155 2114 } 2156 2115 -
trunk/Source/JavaScriptCore/assembler/SH4Assembler.h
r151174 r154016 338 338 339 339 SH4Assembler() 340 {341 m_claimscratchReg = 0x0;340 : m_claimscratchReg(0x0) 341 { 342 342 } 343 343 … … 1190 1190 } 1191 1191 1192 void movlImm8r(int imm8, RegisterID dst)1193 {1194 ASSERT((imm8 <= 127) && (imm8 >= -128));1195 1196 uint16_t opc = getOpcodeGroup3(MOVIMM_OPCODE, dst, imm8);1197 oneShortOp(opc);1198 }1199 1200 1192 void loadConstant(uint32_t constant, RegisterID dst) 1201 1193 { … … 1332 1324 static void changePCrelativeAddress(int offset, uint16_t* instructionPtr, uint32_t newAddress) 1333 1325 { 1326 ASSERT((instructionPtr[0] & 0xf000) == MOVL_READ_OFFPC_OPCODE); 1334 1327 uint32_t address = (offset << 2) + ((reinterpret_cast<uint32_t>(instructionPtr) + 4) &(~0x3)); 1335 1328 *reinterpret_cast<uint32_t*>(address) = newAddress; … … 1338 1331 static uint32_t readPCrelativeAddress(int offset, uint16_t* instructionPtr) 1339 1332 { 1333 ASSERT((instructionPtr[0] & 0xf000) == MOVL_READ_OFFPC_OPCODE); 1340 1334 uint32_t address = (offset << 2) + ((reinterpret_cast<uint32_t>(instructionPtr) + 4) &(~0x3)); 1341 1335 return *reinterpret_cast<uint32_t*>(address); … … 1375 1369 nop nop 1376 1370 */ 1377 ASSERT((*(instructionPtr + 1) & BRAF_OPCODE) == BRAF_OPCODE); 1378 1379 offsetBits -= 4; 1380 if (offsetBits >= -4096 && offsetBits <= 4094) { 1381 *instructionPtr = getOpcodeGroup6(BRA_OPCODE, offsetBits >> 1); 1382 *(++instructionPtr) = NOP_OPCODE; 1383 printBlockInstr(instructionPtr - 1, from.m_offset, 2); 1384 return; 1385 } 1386 1387 changePCrelativeAddress((*instructionPtr & 0xff), instructionPtr, offsetBits - 2); 1371 ASSERT((instructionPtr[0] & 0xf000) == MOVL_READ_OFFPC_OPCODE); 1372 ASSERT((instructionPtr[1] & 0xf0ff) == BRAF_OPCODE); 1373 changePCrelativeAddress((*instructionPtr & 0xff), instructionPtr, offsetBits - 6); 1388 1374 printInstr(*instructionPtr, from.m_offset + 2); 1389 1375 } … … 1393 1379 uint16_t* instructionPtr = getInstructionPtr(code, from.m_offset); 1394 1380 instructionPtr -= 3; 1381 ASSERT((instructionPtr[0] & 0xf000) == MOVL_READ_OFFPC_OPCODE); 1395 1382 changePCrelativeAddress((*instructionPtr & 0xff), instructionPtr, reinterpret_cast<uint32_t>(to)); 1396 1383 } … … 1399 1386 { 1400 1387 uint16_t* instructionPtr = getInstructionPtr(code, where.m_offset); 1388 ASSERT((instructionPtr[0] & 0xf000) == MOVL_READ_OFFPC_OPCODE); 1401 1389 changePCrelativeAddress((*instructionPtr & 0xff), instructionPtr, reinterpret_cast<uint32_t>(value)); 1402 1390 } … … 1442 1430 1443 1431 int offset = reinterpret_cast<uint32_t>(constPoolAddr) + (index * 4) - ((reinterpret_cast<uint32_t>(instructionPtr) & ~0x03) + 4); 1444 instruction &= 0xf00;1432 instruction &= 0x0f00; 1445 1433 instruction |= 0xd000; 1446 1434 offset &= 0x03ff; … … 1463 1451 { 1464 1452 uint16_t* instructionPtr = reinterpret_cast<uint16_t*>(where); 1453 ASSERT((instructionPtr[0] & 0xf000) == MOVL_READ_OFFPC_OPCODE); 1465 1454 changePCrelativeAddress((*instructionPtr & 0xff), instructionPtr, value); 1466 1455 } … … 1478 1467 uint16_t* instructionPtr = reinterpret_cast<uint16_t*>(from); 1479 1468 instructionPtr -= 3; 1469 ASSERT((instructionPtr[0] & 0xf000) == MOVL_READ_OFFPC_OPCODE); 1480 1470 changePCrelativeAddress((*instructionPtr & 0xff), instructionPtr, reinterpret_cast<uint32_t>(to)); 1481 1471 } … … 1490 1480 offsetBits -= 8; 1491 1481 instructionPtr++; 1482 ASSERT((instructionPtr[0] & 0xf000) == MOVL_READ_OFFPC_OPCODE); 1492 1483 changePCrelativeAddress((*instructionPtr & 0xff), instructionPtr, offsetBits); 1493 1484 instruction = (BRAF_OPCODE | (*instructionPtr++ & 0xf00)); 1494 1485 *instructionPtr = instruction; 1495 1486 printBlockInstr(instructionPtr, reinterpret_cast<uint32_t>(from) + 1, 3); 1496 return; 1497 } 1498 1499 ASSERT((*(instructionPtr + 1) & BRAF_OPCODE) == BRAF_OPCODE); 1500 offsetBits -= 4; 1501 if (offsetBits >= -4096 && offsetBits <= 4094) { 1502 *instructionPtr = getOpcodeGroup6(BRA_OPCODE, offsetBits >> 1); 1503 *(++instructionPtr) = NOP_OPCODE; 1504 printBlockInstr(instructionPtr - 2, reinterpret_cast<uint32_t>(from), 2); 1505 return; 1506 } 1507 1508 changePCrelativeAddress((*instructionPtr & 0xff), instructionPtr, offsetBits - 2); 1487 cacheFlush(instructionPtr, sizeof(SH4Word)); 1488 return; 1489 } 1490 1491 ASSERT((instructionPtr[1] & 0xf0ff) == BRAF_OPCODE); 1492 changePCrelativeAddress((*instructionPtr & 0xff), instructionPtr, offsetBits - 6); 1509 1493 printInstr(*instructionPtr, reinterpret_cast<uint32_t>(from)); 1510 1494 } … … 1521 1505 SH4Word* instruction = reinterpret_cast<SH4Word*>(instructionStart); 1522 1506 intptr_t difference = reinterpret_cast<intptr_t>(to) - (reinterpret_cast<intptr_t>(instruction) + 2 * sizeof(SH4Word)); 1523 int nbinst = 0; 1524 1525 if ((difference >= -4096) && (difference <= 4094)) { 1526 instruction[0] = getOpcodeGroup6(BRA_OPCODE, difference >> 1); 1527 instruction[1] = NOP_OPCODE; 1528 cacheFlush(instruction, sizeof(SH4Word) * 2); 1529 return; 1530 } 1531 1532 instruction[nbinst++] = getOpcodeGroup3(MOVL_READ_OFFPC_OPCODE, scratchReg2, 1); 1533 instruction[nbinst++] = getOpcodeGroup2(JMP_OPCODE, scratchReg2); 1534 instruction[nbinst++] = NOP_OPCODE; 1535 1536 if (!(reinterpret_cast<unsigned>(instruction) & 3)) 1537 instruction[nbinst++] = NOP_OPCODE; 1538 1539 instruction[nbinst++] = reinterpret_cast<unsigned>(to) & 0xffff; 1540 instruction[nbinst++] = reinterpret_cast<unsigned>(to) >> 16; 1541 cacheFlush(instruction, sizeof(SH4Word) * nbinst); 1542 } 1543 1544 static void revertJump(void* instructionStart, void *immptr) 1507 1508 if ((instruction[0] & 0xf000) == MOVL_READ_OFFPC_OPCODE) { 1509 instruction[1] = (BRAF_OPCODE | (instruction[0] & 0x0f00)); 1510 instruction[2] = NOP_OPCODE; 1511 cacheFlush(&instruction[1], 2 * sizeof(SH4Word)); 1512 } else { 1513 instruction[0] = getOpcodeGroup3(MOVL_READ_OFFPC_OPCODE, SH4Registers::r13, 1); 1514 instruction[1] = getOpcodeGroup2(BRAF_OPCODE, SH4Registers::r13); 1515 instruction[2] = NOP_OPCODE; 1516 cacheFlush(instruction, 3 * sizeof(SH4Word)); 1517 } 1518 1519 changePCrelativeAddress(instruction[0] & 0x00ff, instruction, difference - 2); 1520 } 1521 1522 static void revertJumpToMove(void* instructionStart, RegisterID rd, int imm) 1545 1523 { 1546 1524 SH4Word *insn = reinterpret_cast<SH4Word*>(instructionStart); 1547 1525 ASSERT((insn[0] & 0xf000) == MOVL_READ_OFFPC_OPCODE); 1548 changePCrelativeAddress(insn[0] & 0x00ff, insn, reinterpret_cast<uint32_t>(immptr)); 1526 1527 if ((insn[1] & 0xf000) == CMPEQ_OPCODE) { 1528 insn[0] = getOpcodeGroup3(MOVL_READ_OFFPC_OPCODE, SH4Registers::r13, insn[0] & 0x00ff); 1529 insn[1] = (insn[1] & 0xf00f) | (rd << 8) | (SH4Registers::r13 << 4); 1530 cacheFlush(insn, 2 * sizeof(SH4Word)); 1531 changePCrelativeAddress(insn[0] & 0x00ff, insn, imm); 1532 return; 1533 } 1534 1535 if ((insn[0] & 0x00ff) == 1) 1536 insn[1] = getOpcodeGroup6(BRA_OPCODE, 3); 1537 else 1538 insn[1] = NOP_OPCODE; 1539 1540 insn[2] = NOP_OPCODE; 1541 cacheFlush(&insn[1], 2 * sizeof(SH4Word)); 1542 1543 changePCrelativeAddress(insn[0] & 0x00ff, insn, imm); 1549 1544 } 1550 1545 … … 1559 1554 1560 1555 if (type == JumpNear) { 1561 ASSERT((instruction == BT_OPCODE) || (instruction == BF_OPCODE) || (instruction == BRA_OPCODE));1562 1556 int offset = (codeSize() - from.m_offset) - 4; 1557 ASSERT((((instruction == BT_OPCODE) || (instruction == BF_OPCODE)) && (offset >= -256) && (offset <= 254)) 1558 || ((instruction == BRA_OPCODE) && (offset >= -4096) && (offset <= 4094))); 1563 1559 *instructionPtr++ = instruction | (offset >> 1); 1564 1560 printInstr(*instructionPtr, from.m_offset + 2); … … 1575 1571 instruction ^= 0x0202; 1576 1572 *instructionPtr++ = instruction; 1577 if ((*instructionPtr & 0xf000) == 0xe000) {1573 if ((*instructionPtr & 0xf000) == MOVIMM_OPCODE) { 1578 1574 uint32_t* addr = getLdrImmAddressOnPool(instructionPtr, m_buffer.poolAddress()); 1579 1575 *addr = offsetBits; … … 1591 1587 */ 1592 1588 ASSERT((*(instructionPtr + 1) & BRAF_OPCODE) == BRAF_OPCODE); 1593 offsetBits = (to.m_offset - from.m_offset) - 4; 1594 if (offsetBits >= -4096 && offsetBits <= 4094) { 1595 *instructionPtr = getOpcodeGroup6(BRA_OPCODE, offsetBits >> 1); 1596 *(++instructionPtr) = NOP_OPCODE; 1597 printBlockInstr(instructionPtr - 1, from.m_offset, 2); 1598 return; 1599 } 1589 offsetBits = (to.m_offset - from.m_offset) - 6; 1600 1590 1601 1591 instruction = *instructionPtr; 1602 if ((instruction & 0xf000) == 0xe000) {1592 if ((instruction & 0xf000) == MOVIMM_OPCODE) { 1603 1593 uint32_t* addr = getLdrImmAddressOnPool(instructionPtr, m_buffer.poolAddress()); 1604 *addr = offsetBits - 2;1594 *addr = offsetBits; 1605 1595 printInstr(*instructionPtr, from.m_offset + 2); 1606 1596 return; 1607 1597 } 1608 1598 1609 changePCrelativeAddress((*instructionPtr & 0xff), instructionPtr, offsetBits - 2); 1599 ASSERT((instructionPtr[0] & 0xf000) == MOVL_READ_OFFPC_OPCODE); 1600 changePCrelativeAddress((*instructionPtr & 0xff), instructionPtr, offsetBits); 1610 1601 printInstr(*instructionPtr, from.m_offset + 2); 1611 1602 } -
trunk/Source/JavaScriptCore/jit/JITStubs.cpp
r153962 r154016 115 115 #elif CPU(MIPS) 116 116 performMIPSJITAssertions(); 117 #elif CPU(SH4) 118 performSH4JITAssertions(); 117 119 #endif 118 120 } -
trunk/Source/JavaScriptCore/jit/JITStubs.h
r153646 r154016 267 267 268 268 ReturnAddressPtr thunkReturnAddress; 269 269 270 void* savedR10; 270 271 void* savedR11; … … 273 274 void* savedR14; 274 275 276 // These arguments are passed in r5, r6 and r7. 275 277 JSStack* stack; 276 278 CallFrame* callFrame; 277 279 JSValue* exception; 280 281 // These arguments are passed on the stack. 278 282 void* unused1; 279 283 VM* vm; -
trunk/Source/JavaScriptCore/jit/JITStubsSH4.h
r153583 r154016 42 42 namespace JSC { 43 43 44 #define THUNK_RETURN_ADDRESS_OFFSET 56 45 #define SAVED_R8_OFFSET 60 46 44 47 #define SYMBOL_STRING(name) #name 45 48 /* code (r4), JSStack* (r5), CallFrame* (r6), void* unused1 (r7), void* unused2(sp), VM (sp)*/ … … 58 61 "mov.l r11, @-r15" "\n" 59 62 "mov.l r10, @-r15" "\n" 60 "add #- 60, r15" "\n"63 "add #-" STRINGIZE_VALUE_OF(SAVED_R8_OFFSET) ", r15" "\n" 61 64 "mov r6, r14" "\n" 62 65 "jsr @r4" "\n" 63 66 "nop" "\n" 64 "add # 60, r15" "\n"67 "add #" STRINGIZE_VALUE_OF(SAVED_R8_OFFSET) ", r15" "\n" 65 68 "mov.l @r15+,r10" "\n" 66 69 "mov.l @r15+,r11" "\n" … … 85 88 "jsr @r11" "\n" 86 89 "nop" "\n" 87 "add # 60, r15" "\n"90 "add #" STRINGIZE_VALUE_OF(SAVED_R8_OFFSET) ", r15" "\n" 88 91 "mov.l @r15+,r10" "\n" 89 92 "mov.l @r15+,r11" "\n" … … 109 112 "nop" "\n" 110 113 "mov r0, r14" "\n" 111 "jmp @r1" "\n" 114 "lds r1, pr" "\n" 115 "rts" "\n" 112 116 "nop" "\n" 113 117 ".align 2" "\n" … … 119 123 HIDE_SYMBOL(ctiOpThrowNotCaught) "\n" 120 124 SYMBOL_STRING(ctiOpThrowNotCaught) ":" "\n" 121 "add # 60, r15" "\n"125 "add #" STRINGIZE_VALUE_OF(SAVED_R8_OFFSET) ", r15" "\n" 122 126 "mov.l @r15+,r10" "\n" 123 127 "mov.l @r15+,r11" "\n" … … 140 144 SYMBOL_STRING(cti_##op) ":" "\n" \ 141 145 "sts pr, r11" "\n" \ 142 "mov.l r11, @( 0x38, r15)" "\n" \146 "mov.l r11, @(" STRINGIZE_VALUE_OF(THUNK_RETURN_ADDRESS_OFFSET) ", r15)" "\n" \ 143 147 "mov.l .L2"SYMBOL_STRING(JITStubThunked_##op)",r0" "\n" \ 144 148 "mov.l @(r0,r12),r11" "\n" \ 145 149 "jsr @r11" "\n" \ 146 150 "nop" "\n" \ 147 "mov.l @( 0x38, r15), r11 " "\n" \151 "mov.l @(" STRINGIZE_VALUE_OF(THUNK_RETURN_ADDRESS_OFFSET) ", r15), r11 " "\n" \ 148 152 "lds r11, pr " "\n" \ 149 153 "rts" "\n" \ … … 154 158 rtype JITStubThunked_##op(STUB_ARGS_DECLARATION) 155 159 160 static void performSH4JITAssertions() 161 { 162 ASSERT(OBJECT_OFFSETOF(struct JITStackFrame, thunkReturnAddress) == THUNK_RETURN_ADDRESS_OFFSET); 163 ASSERT(OBJECT_OFFSETOF(struct JITStackFrame, savedR8) == SAVED_R8_OFFSET); 164 } 165 156 166 } // namespace JSC 157 167 -
trunk/Source/JavaScriptCore/jit/JSInterfaceJIT.h
r153371 r154016 165 165 static const RegisterID cachedResultRegister = SH4Registers::r0; 166 166 167 static const FPRegisterID fpRegT0 = SH4Registers::fr0; 168 static const FPRegisterID fpRegT1 = SH4Registers::fr2; 169 static const FPRegisterID fpRegT2 = SH4Registers::fr4; 170 static const FPRegisterID fpRegT3 = SH4Registers::fr6; 171 static const FPRegisterID fpRegT4 = SH4Registers::fr8; 172 static const FPRegisterID fpRegT5 = SH4Registers::fr10; 173 static const FPRegisterID fpRegT6 = SH4Registers::fr12; 174 static const FPRegisterID fpRegT7 = SH4Registers::fr14; 167 static const FPRegisterID fpRegT0 = SH4Registers::dr0; 168 static const FPRegisterID fpRegT1 = SH4Registers::dr2; 169 static const FPRegisterID fpRegT2 = SH4Registers::dr4; 170 static const FPRegisterID fpRegT3 = SH4Registers::dr6; 171 static const FPRegisterID fpRegT4 = SH4Registers::dr8; 172 static const FPRegisterID fpRegT5 = SH4Registers::dr10; 175 173 #else 176 174 #error "JIT not supported on this platform."
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