Changeset 158580 in webkit


Ignore:
Timestamp:
Nov 4, 2013 10:21:37 AM (10 years ago)
Author:
commit-queue@webkit.org
Message:

[sh4] Refactor jumps in baseline JIT to return label after the jump.
​https://bugs.webkit.org/show_bug.cgi?id=123734

Patch by Julien Brianceau <​jbriance@cisco.com> on 2013-11-04
Reviewed by Michael Saboff.

Current implementation of jumps in sh4 baseline JIT returns a label on the jump itself
and not after it. This is not correct and leads to issues like infinite loop the DFG
(​https://bugs.webkit.org/show_bug.cgi?id=122597 for instance). This refactor fixes this
and also simplifies the link and relink procedures for sh4 jumps.

  • assembler/MacroAssemblerSH4.h:

(JSC::MacroAssemblerSH4::branchDouble):
(JSC::MacroAssemblerSH4::branchTrue):
(JSC::MacroAssemblerSH4::branchFalse):

  • assembler/SH4Assembler.h:

(JSC::SH4Assembler::jmp):
(JSC::SH4Assembler::extraInstrForBranch):
(JSC::SH4Assembler::jne):
(JSC::SH4Assembler::je):
(JSC::SH4Assembler::bra):
(JSC::SH4Assembler::linkJump):
(JSC::SH4Assembler::relinkJump):

Location:
trunk/Source/JavaScriptCore
Files:
3 edited

Legend:

Unmodified
Added
Removed

  • trunk/Source/JavaScriptCore/ChangeLog

    r158556 r158580  
     12013-11-04  Julien Brianceau  <jbriance@cisco.com>
     2
     3        [sh4] Refactor jumps in baseline JIT to return label after the jump.
     4        https://bugs.webkit.org/show_bug.cgi?id=123734
     5
     6        Reviewed by Michael Saboff.
     7
     8        Current implementation of jumps in sh4 baseline JIT returns a label on the jump itself
     9        and not after it. This is not correct and leads to issues like infinite loop the DFG
     10        (https://bugs.webkit.org/show_bug.cgi?id=122597 for instance). This refactor fixes this
     11        and also simplifies the link and relink procedures for sh4 jumps.
     12
     13        * assembler/MacroAssemblerSH4.h:
     14        (JSC::MacroAssemblerSH4::branchDouble):
     15        (JSC::MacroAssemblerSH4::branchTrue):
     16        (JSC::MacroAssemblerSH4::branchFalse):
     17        * assembler/SH4Assembler.h:
     18        (JSC::SH4Assembler::jmp):
     19        (JSC::SH4Assembler::extraInstrForBranch):
     20        (JSC::SH4Assembler::jne):
     21        (JSC::SH4Assembler::je):
     22        (JSC::SH4Assembler::bra):
     23        (JSC::SH4Assembler::linkJump):
     24        (JSC::SH4Assembler::relinkJump):
     25
    1262013-11-03  Filip Pizlo  <fpizlo@apple.com>
    227

  • trunk/Source/JavaScriptCore/assembler/MacroAssemblerSH4.h

    r157334 r158580  
    14551455            takeBranch.append(Jump(m_assembler.jne(), SH4Assembler::JumpNear));
    14561456            m_assembler.dcmppeq(left, right);
    1457             Jump m_jump = Jump(m_assembler.je());
     1457            m_assembler.branch(BF_OPCODE, 2);
    14581458            takeBranch.link(this);
    1459             m_assembler.extraInstrForBranch(scratchReg3);
    1460             return m_jump;
     1459            return Jump(m_assembler.extraInstrForBranch(scratchReg3));
    14611460        }
    14621461
    … …  
    14691468            takeBranch.append(Jump(m_assembler.jne(), SH4Assembler::JumpNear));
    14701469            m_assembler.dcmppgt(right, left);
    1471             Jump m_jump = Jump(m_assembler.je());
     1470            m_assembler.branch(BF_OPCODE, 2);
    14721471            takeBranch.link(this);
    1473             m_assembler.extraInstrForBranch(scratchReg3);
    1474             return m_jump;
     1472            return Jump(m_assembler.extraInstrForBranch(scratchReg3));
    14751473        }
    14761474
    … …  
    14881486            takeBranch.append(Jump(m_assembler.jne(), SH4Assembler::JumpNear));
    14891487            m_assembler.dcmppgt(left, right);
    1490             Jump m_jump = Jump(m_assembler.je());
     1488            m_assembler.branch(BF_OPCODE, 2);
    14911489            takeBranch.link(this);
    1492             m_assembler.extraInstrForBranch(scratchReg3);
    1493             return m_jump;
     1490            return Jump(m_assembler.extraInstrForBranch(scratchReg3));
    14941491        }
    14951492
    … …  
    15071504    {
    15081505        m_assembler.ensureSpace(m_assembler.maxInstructionSize + 6, sizeof(uint32_t));
    1509         Jump m_jump = Jump(m_assembler.je());
    1510         m_assembler.extraInstrForBranch(scratchReg3);
    1511         return m_jump;
     1506        m_assembler.branch(BF_OPCODE, 2);
     1507        return Jump(m_assembler.extraInstrForBranch(scratchReg3));
    15121508    }
    15131509
    … …  
    15151511    {
    15161512        m_assembler.ensureSpace(m_assembler.maxInstructionSize + 6, sizeof(uint32_t));
    1517         Jump m_jump = Jump(m_assembler.jne());
    1518         m_assembler.extraInstrForBranch(scratchReg3);
    1519         return m_jump;
     1513        m_assembler.branch(BT_OPCODE, 2);
     1514        return Jump(m_assembler.extraInstrForBranch(scratchReg3));
    15201515    }
    15211516

  • trunk/Source/JavaScriptCore/assembler/SH4Assembler.h

    r157796 r158580  
    12521252        RegisterID scr = claimScratch();
    12531253        m_buffer.ensureSpace(maxInstructionSize + 4, sizeof(uint32_t));
    1254         AssemblerLabel label = m_buffer.label();
    12551254        loadConstantUnReusable(0x0, scr);
    12561255        branch(BRAF_OPCODE, scr);
    12571256        nop();
    12581257        releaseScratch(scr);
    1259         return label;
    1260     }
    1261 
    1262     void extraInstrForBranch(RegisterID dst)
     1258        return m_buffer.label();
     1259    }
     1260
     1261    AssemblerLabel extraInstrForBranch(RegisterID dst)
    12631262    {
    12641263        loadConstantUnReusable(0x0, dst);
     1264        branch(BRAF_OPCODE, dst);
    12651265        nop();
    1266         nop();
     1266        return m_buffer.label();
    12671267    }
    12681268
    … …  
    12821282    AssemblerLabel jne()
    12831283    {
    1284         AssemblerLabel label = m_buffer.label();
    12851284        branch(BF_OPCODE, 0);
    1286         return label;
     1285        return m_buffer.label();
    12871286    }
    12881287
    12891288    AssemblerLabel je()
    12901289    {
    1291         AssemblerLabel label = m_buffer.label();
    12921290        branch(BT_OPCODE, 0);
    1293         return label;
     1291        return m_buffer.label();
    12941292    }
    12951293
    12961294    AssemblerLabel bra()
    12971295    {
    1298         AssemblerLabel label = m_buffer.label();
    12991296        branch(BRA_OPCODE, 0);
    1300         return label;
     1297        return m_buffer.label();
    13011298    }
    13021299
    … …  
    13721369        ASSERT(from.isSet());
    13731370
    1374         uint16_t* instructionPtr = getInstructionPtr(code, from.m_offset);
    1375         uint16_t instruction = *instructionPtr;
     1371        uint16_t* instructionPtr = getInstructionPtr(code, from.m_offset) - 3;
    13761372        int offsetBits = (reinterpret_cast<uint32_t>(to) - reinterpret_cast<uint32_t>(code)) - from.m_offset;
    13771373
    1378         if (((instruction & 0xff00) == BT_OPCODE) || ((instruction & 0xff00) == BF_OPCODE)) {
    1379             /* BT label ==> BF 2
    1380                nop          LDR reg
    1381                nop          braf @reg
    1382                nop          nop
    1383             */
    1384             offsetBits -= 8;
    1385             instruction ^= 0x0202;
    1386             *instructionPtr++ = instruction;
    1387             changePCrelativeAddress((*instructionPtr & 0xff), instructionPtr, offsetBits);
    1388             instruction = (BRAF_OPCODE | (*instructionPtr++ & 0xf00));
    1389             *instructionPtr = instruction;
    1390             printBlockInstr(instructionPtr - 2, from.m_offset, 3);
    1391             return;
    1392         }
    1393 
    1394          /* MOV #imm, reg => LDR reg
    1395             braf @reg        braf @reg
    1396             nop              nop
    1397          */
     1374        /* MOV #imm, reg => LDR reg
     1375           braf @reg        braf @reg
     1376           nop              nop
     1377        */
    13981378        ASSERT((instructionPtr[0] & 0xf000) == MOVL_READ_OFFPC_OPCODE);
    13991379        ASSERT((instructionPtr[1] & 0xf0ff) == BRAF_OPCODE);
    1400         changePCrelativeAddress((*instructionPtr & 0xff), instructionPtr, offsetBits - 6);
     1380        changePCrelativeAddress((*instructionPtr & 0xff), instructionPtr, offsetBits);
    14011381        printInstr(*instructionPtr, from.m_offset + 2);
    14021382    }
    … …  
    15011481    {
    15021482        uint16_t* instructionPtr = reinterpret_cast<uint16_t*> (from);
    1503         uint16_t instruction = *instructionPtr;
    1504         int32_t offsetBits = (reinterpret_cast<uint32_t>(to) - reinterpret_cast<uint32_t>(from));
    1505 
    1506         if (((*instructionPtr & 0xff00) == BT_OPCODE) || ((*instructionPtr & 0xff00) == BF_OPCODE)) {
    1507             offsetBits -= 8;
    1508             instructionPtr++;
    1509             ASSERT((instructionPtr[0] & 0xf000) == MOVL_READ_OFFPC_OPCODE);
    1510             changePCrelativeAddress((*instructionPtr & 0xff), instructionPtr, offsetBits);
    1511             instruction = (BRAF_OPCODE | (*instructionPtr++ & 0xf00));
    1512             *instructionPtr = instruction;
    1513             printBlockInstr(instructionPtr, reinterpret_cast<uint32_t>(from) + 1, 3);
    1514             cacheFlush(instructionPtr, sizeof(SH4Word));
    1515             return;
    1516         }
    1517 
     1483        instructionPtr -= 3;
     1484        ASSERT((instructionPtr[0] & 0xf000) == MOVL_READ_OFFPC_OPCODE);
    15181485        ASSERT((instructionPtr[1] & 0xf0ff) == BRAF_OPCODE);
    1519         changePCrelativeAddress((*instructionPtr & 0xff), instructionPtr, offsetBits - 6);
    1520         printInstr(*instructionPtr, reinterpret_cast<uint32_t>(from));
     1486        changePCrelativeAddress((*instructionPtr & 0xff), instructionPtr, reinterpret_cast<uint32_t>(to) - reinterpret_cast<uint32_t>(from));
    15211487    }
    15221488
    … …  
    15701536        ASSERT(from.isSet());
    15711537
    1572         uint16_t* instructionPtr = getInstructionPtr(data(), from.m_offset);
    1573         uint16_t instruction = *instructionPtr;
    1574         int offsetBits;
     1538        uint16_t* instructionPtr = getInstructionPtr(data(), from.m_offset) - 1;
     1539        int offsetBits = (to.m_offset - from.m_offset);
    15751540
    15761541        if (type == JumpNear) {
    1577             int offset = (codeSize() - from.m_offset) - 4;
     1542            uint16_t instruction = instructionPtr[0];
     1543            int offset = (offsetBits - 2);
    15781544            ASSERT((((instruction == BT_OPCODE) || (instruction == BF_OPCODE)) && (offset >= -256) && (offset <= 254))
    15791545                || ((instruction == BRA_OPCODE) && (offset >= -4096) && (offset <= 4094)));
    … …  
    15831549        }
    15841550
    1585         if (((instruction & 0xff00) == BT_OPCODE) || ((instruction & 0xff00) == BF_OPCODE)) {
    1586             /* BT label => BF 2
    1587                nop        LDR reg
    1588                nop        braf @reg
    1589                nop        nop
    1590             */
    1591             offsetBits = (to.m_offset - from.m_offset) - 8;
    1592             instruction ^= 0x0202;
    1593             *instructionPtr++ = instruction;
    1594             if ((*instructionPtr & 0xf000) == MOVIMM_OPCODE) {
    1595                 uint32_t* addr = getLdrImmAddressOnPool(instructionPtr, m_buffer.poolAddress());
    1596                 *addr = offsetBits;
    1597             } else
    1598                 changePCrelativeAddress((*instructionPtr & 0xff), instructionPtr, offsetBits);
    1599             instruction = (BRAF_OPCODE | (*instructionPtr++ & 0xf00));
    1600             *instructionPtr = instruction;
    1601             printBlockInstr(instructionPtr - 2, from.m_offset, 3);
    1602             return;
    1603         }
    1604 
    16051551        /* MOV # imm, reg => LDR reg
    16061552           braf @reg         braf @reg
    16071553           nop               nop
    16081554        */
    1609         ASSERT((*(instructionPtr + 1) & BRAF_OPCODE) == BRAF_OPCODE);
    1610         offsetBits = (to.m_offset - from.m_offset) - 6;
    1611 
    1612         instruction = *instructionPtr;
    1613         if ((instruction & 0xf000) == MOVIMM_OPCODE) {
     1555        instructionPtr -= 2;
     1556        ASSERT((instructionPtr[1] & 0xf0ff) == BRAF_OPCODE);
     1557
     1558        if ((instructionPtr[0] & 0xf000) == MOVIMM_OPCODE) {
    16141559            uint32_t* addr = getLdrImmAddressOnPool(instructionPtr, m_buffer.poolAddress());
    16151560            *addr = offsetBits;
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