Changeset 195182 in webkit

Timestamp:

Jan 17, 2016 1:15:45 AM (8 years ago)

Author:

Julien Brianceau

Message:

[mips] Fix regT2 and regT3 trampling in MacroAssembler
​https://bugs.webkit.org/show_bug.cgi?id=153131

Mips $t2 and $t3 registers were used as temporary registers
in MacroAssemblerMIPS.h, whereas they are mapped to regT2
and regT3 in LLInt and GPRInfo.

This patch rearranges register mapping for the mips architecture:

• use $t0 and $t1 as temp registers in LLInt (as in MacroAssembler)
• use $t7 and $t8 as temp registers in MacroAssembler (as in LLInt)
• remove $t6 from temp registers list in LLInt
• update GPRInfo.h accordingly
• add mips macroScratchRegisters() list in RegisterSet.cpp

Reviewed by Michael Saboff.

• assembler/MacroAssemblerMIPS.h:
• jit/GPRInfo.h:

(JSC::GPRInfo::toRegister):
(JSC::GPRInfo::toIndex):

• jit/RegisterSet.cpp:

(JSC::RegisterSet::macroScratchRegisters):
(JSC::RegisterSet::calleeSaveRegisters):

• offlineasm/mips.rb:

Location:

trunk/Source/JavaScriptCore

Files:

• ChangeLog (modified) (1 diff)
• assembler/MacroAssemblerMIPS.h (modified) (1 diff)
• jit/GPRInfo.h (modified) (4 diffs)
• jit/RegisterSet.cpp (modified) (2 diffs)
• offlineasm/mips.rb (modified) (2 diffs)

trunk/Source/JavaScriptCore/ChangeLog

@@ +1 @@
+2016-01-17  Julien Brianceau  <jbriance@cisco.com>
+
+        [mips] Fix regT2 and regT3 trampling in MacroAssembler
+        https://bugs.webkit.org/show_bug.cgi?id=153131
+
+        Mips $t2 and $t3 registers were used as temporary registers
+        in MacroAssemblerMIPS.h, whereas they are mapped to regT2
+        and regT3 in LLInt and GPRInfo.
+
+        This patch rearranges register mapping for the mips architecture:
+        - use $t0 and $t1 as temp registers in LLInt (as in MacroAssembler)
+        - use $t7 and $t8 as temp registers in MacroAssembler (as in LLInt)
+        - remove $t6 from temp registers list in LLInt
+        - update GPRInfo.h accordingly
+        - add mips macroScratchRegisters() list in RegisterSet.cpp
+
+        Reviewed by Michael Saboff.
+
+        * assembler/MacroAssemblerMIPS.h:
+        * jit/GPRInfo.h:
+        (JSC::GPRInfo::toRegister):
+        (JSC::GPRInfo::toIndex):
+        * jit/RegisterSet.cpp:
+        (JSC::RegisterSet::macroScratchRegisters):
+        (JSC::RegisterSet::calleeSaveRegisters):
+        * offlineasm/mips.rb:
+
 2016-01-16  Skachkov Oleksandr  <gskachkov@gmail.com>
 

trunk/Source/JavaScriptCore/assembler/MacroAssemblerMIPS.h

@@ -56 +56 @@
     static const RegisterID dataTempRegister = MIPSRegisters::t1;
     // For storing address base
-    static const RegisterID addrTempRegister = MIPSRegisters::t2;
+    static const RegisterID addrTempRegister = MIPSRegisters::t7;
     // For storing compare result
-    static const RegisterID cmpTempRegister = MIPSRegisters::t3;
+    static const RegisterID cmpTempRegister = MIPSRegisters::t8;
 
     // FP temp register

trunk/Source/JavaScriptCore/jit/GPRInfo.h

@@ -737 +737 @@
 public:
     typedef GPRReg RegisterType;
-    static const unsigned numberOfRegisters = 8;
+    static const unsigned numberOfRegisters = 7;
     static const unsigned numberOfArgumentRegisters = NUMBER_OF_ARGUMENT_REGISTERS;
 
@@ -750 +750 @@
     static const GPRReg regT4 = MIPSRegisters::t4;
     static const GPRReg regT5 = MIPSRegisters::t5;
-    static const GPRReg regT6 = MIPSRegisters::t0;
-    static const GPRReg regT7 = MIPSRegisters::t1;
+    static const GPRReg regT6 = MIPSRegisters::t6;
     // These registers match the baseline JIT.
     static const GPRReg callFrameRegister = MIPSRegisters::fp;
@@ -767 +766 @@
     {
         ASSERT(index < numberOfRegisters);
-        static const GPRReg registerForIndex[numberOfRegisters] = { regT0, regT1, regT2, regT3, regT4, regT5, regT6, regT7 };
+        static const GPRReg registerForIndex[numberOfRegisters] = { regT0, regT1, regT2, regT3, regT4, regT5, regT6 };
         return registerForIndex[index];
     }
@@ -781 +780 @@
     {
         ASSERT(reg != InvalidGPRReg);
-        ASSERT(reg < 24);
-        static const unsigned indexForRegister[24] = {
+        ASSERT(reg < 32);
+        static const unsigned indexForRegister[32] = {
             InvalidIndex, InvalidIndex, 0, 1, InvalidIndex, InvalidIndex, InvalidIndex, InvalidIndex,
-            6, 7, 2, 3, 4, 5, InvalidIndex, InvalidIndex,
+            InvalidIndex, InvalidIndex, 2, 3, 4, 5, 6, InvalidIndex,
+            InvalidIndex, InvalidIndex, InvalidIndex, InvalidIndex, InvalidIndex, InvalidIndex, InvalidIndex, InvalidIndex,
             InvalidIndex, InvalidIndex, InvalidIndex, InvalidIndex, InvalidIndex, InvalidIndex, InvalidIndex, InvalidIndex
         };

trunk/Source/JavaScriptCore/jit/RegisterSet.cpp

@@ -87 +87 @@
 #elif CPU(ARM64)
     return RegisterSet(MacroAssembler::dataTempRegister, MacroAssembler::memoryTempRegister);
+#elif CPU(MIPS)
+    RegisterSet result;
+    result.set(MacroAssembler::immTempRegister);
+    result.set(MacroAssembler::dataTempRegister);
+    result.set(MacroAssembler::addrTempRegister);
+    result.set(MacroAssembler::cmpTempRegister);
+    return result;
 #else
     return RegisterSet();
@@ -142 +149 @@
         reg = static_cast<ARM64Registers::FPRegisterID>(reg + 1))
         result.set(reg);
+#elif CPU(MIPS)
 #else
     UNREACHABLE_FOR_PLATFORM();

trunk/Source/JavaScriptCore/offlineasm/mips.rb

@@ -33 +33 @@
 # $v0 => t0, r0
 # $v1 => t1, r1
+# $t0 =>            (scratch)
+# $t1 =>            (scratch)
 # $t2 =>         t2
 # $t3 =>         t3
 # $t4 =>         t4
 # $t5 =>         t5
-# $t6 =>            (scratch)
+# $t6 =>         t6
 # $t7 =>            (scratch)
 # $t8 =>            (scratch)
@@ -93 +95 @@
 end
 
-MIPS_TEMP_GPRS = [SpecialRegister.new("$t6"), SpecialRegister.new("$t7"), SpecialRegister.new("$t8")]
+MIPS_TEMP_GPRS = [SpecialRegister.new("$t0"), SpecialRegister.new("$t1"), SpecialRegister.new("$t7"), SpecialRegister.new("$t8")]
 MIPS_ZERO_REG = SpecialRegister.new("$zero")
 MIPS_GP_REG = SpecialRegister.new("$gp")