Changeset 55500 in webkit
- Timestamp:
- Mar 3, 2010 7:57:34 PM (14 years ago)
- Location:
- trunk/JavaScriptCore
- Files:
-
- 2 added
- 6 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/JavaScriptCore/ChangeLog
r55495 r55500 1 2010-03-03 Chao-ying Fu <fu@mips.com> 2 3 Reviewed by Gavin Barraclough. 4 5 MIPS JIT Supports 6 https://bugs.webkit.org/show_bug.cgi?id=30144 7 8 The following changes enable MIPS YARR and YARR_JIT. 9 10 * assembler/AbstractMacroAssembler.h: 11 (JSC::AbstractMacroAssembler::Imm32::Imm32): 12 * assembler/MIPSAssembler.h: Added. 13 (JSC::MIPSRegisters::): 14 (JSC::MIPSAssembler::MIPSAssembler): 15 (JSC::MIPSAssembler::): 16 (JSC::MIPSAssembler::JmpSrc::JmpSrc): 17 (JSC::MIPSAssembler::JmpDst::JmpDst): 18 (JSC::MIPSAssembler::JmpDst::isUsed): 19 (JSC::MIPSAssembler::JmpDst::used): 20 (JSC::MIPSAssembler::emitInst): 21 (JSC::MIPSAssembler::nop): 22 (JSC::MIPSAssembler::loadDelayNop): 23 (JSC::MIPSAssembler::copDelayNop): 24 (JSC::MIPSAssembler::move): 25 (JSC::MIPSAssembler::li): 26 (JSC::MIPSAssembler::lui): 27 (JSC::MIPSAssembler::addiu): 28 (JSC::MIPSAssembler::addu): 29 (JSC::MIPSAssembler::subu): 30 (JSC::MIPSAssembler::mult): 31 (JSC::MIPSAssembler::mfhi): 32 (JSC::MIPSAssembler::mflo): 33 (JSC::MIPSAssembler::mul): 34 (JSC::MIPSAssembler::andInsn): 35 (JSC::MIPSAssembler::andi): 36 (JSC::MIPSAssembler::nor): 37 (JSC::MIPSAssembler::orInsn): 38 (JSC::MIPSAssembler::ori): 39 (JSC::MIPSAssembler::xorInsn): 40 (JSC::MIPSAssembler::xori): 41 (JSC::MIPSAssembler::slt): 42 (JSC::MIPSAssembler::sltu): 43 (JSC::MIPSAssembler::sltiu): 44 (JSC::MIPSAssembler::sll): 45 (JSC::MIPSAssembler::sllv): 46 (JSC::MIPSAssembler::sra): 47 (JSC::MIPSAssembler::srav): 48 (JSC::MIPSAssembler::lw): 49 (JSC::MIPSAssembler::lwl): 50 (JSC::MIPSAssembler::lwr): 51 (JSC::MIPSAssembler::lhu): 52 (JSC::MIPSAssembler::sw): 53 (JSC::MIPSAssembler::jr): 54 (JSC::MIPSAssembler::jalr): 55 (JSC::MIPSAssembler::jal): 56 (JSC::MIPSAssembler::bkpt): 57 (JSC::MIPSAssembler::bgez): 58 (JSC::MIPSAssembler::bltz): 59 (JSC::MIPSAssembler::beq): 60 (JSC::MIPSAssembler::bne): 61 (JSC::MIPSAssembler::bc1t): 62 (JSC::MIPSAssembler::bc1f): 63 (JSC::MIPSAssembler::newJmpSrc): 64 (JSC::MIPSAssembler::appendJump): 65 (JSC::MIPSAssembler::addd): 66 (JSC::MIPSAssembler::subd): 67 (JSC::MIPSAssembler::muld): 68 (JSC::MIPSAssembler::lwc1): 69 (JSC::MIPSAssembler::ldc1): 70 (JSC::MIPSAssembler::swc1): 71 (JSC::MIPSAssembler::sdc1): 72 (JSC::MIPSAssembler::mtc1): 73 (JSC::MIPSAssembler::mfc1): 74 (JSC::MIPSAssembler::truncwd): 75 (JSC::MIPSAssembler::cvtdw): 76 (JSC::MIPSAssembler::ceqd): 77 (JSC::MIPSAssembler::cngtd): 78 (JSC::MIPSAssembler::cnged): 79 (JSC::MIPSAssembler::cltd): 80 (JSC::MIPSAssembler::cled): 81 (JSC::MIPSAssembler::cueqd): 82 (JSC::MIPSAssembler::coled): 83 (JSC::MIPSAssembler::coltd): 84 (JSC::MIPSAssembler::culed): 85 (JSC::MIPSAssembler::cultd): 86 (JSC::MIPSAssembler::label): 87 (JSC::MIPSAssembler::align): 88 (JSC::MIPSAssembler::getRelocatedAddress): 89 (JSC::MIPSAssembler::getDifferenceBetweenLabels): 90 (JSC::MIPSAssembler::size): 91 (JSC::MIPSAssembler::executableCopy): 92 (JSC::MIPSAssembler::getCallReturnOffset): 93 (JSC::MIPSAssembler::linkJump): 94 (JSC::MIPSAssembler::linkCall): 95 (JSC::MIPSAssembler::linkPointer): 96 (JSC::MIPSAssembler::relinkJump): 97 (JSC::MIPSAssembler::relinkCall): 98 (JSC::MIPSAssembler::repatchInt32): 99 (JSC::MIPSAssembler::repatchPointer): 100 (JSC::MIPSAssembler::repatchLoadPtrToLEA): 101 (JSC::MIPSAssembler::relocateJumps): 102 (JSC::MIPSAssembler::linkWithOffset): 103 (JSC::MIPSAssembler::linkCallInternal): 104 * assembler/MacroAssembler.h: 105 * assembler/MacroAssemblerMIPS.h: Added. 106 (JSC::MacroAssemblerMIPS::MacroAssemblerMIPS): 107 (JSC::MacroAssemblerMIPS::): 108 (JSC::MacroAssemblerMIPS::add32): 109 (JSC::MacroAssemblerMIPS::and32): 110 (JSC::MacroAssemblerMIPS::lshift32): 111 (JSC::MacroAssemblerMIPS::mul32): 112 (JSC::MacroAssemblerMIPS::not32): 113 (JSC::MacroAssemblerMIPS::or32): 114 (JSC::MacroAssemblerMIPS::rshift32): 115 (JSC::MacroAssemblerMIPS::sub32): 116 (JSC::MacroAssemblerMIPS::xor32): 117 (JSC::MacroAssemblerMIPS::load32): 118 (JSC::MacroAssemblerMIPS::load32WithUnalignedHalfWords): 119 (JSC::MacroAssemblerMIPS::load32WithAddressOffsetPatch): 120 (JSC::MacroAssemblerMIPS::loadPtrWithPatchToLEA): 121 (JSC::MacroAssemblerMIPS::loadPtrWithAddressOffsetPatch): 122 (JSC::MacroAssemblerMIPS::load16): 123 (JSC::MacroAssemblerMIPS::store32WithAddressOffsetPatch): 124 (JSC::MacroAssemblerMIPS::store32): 125 (JSC::MacroAssemblerMIPS::supportsFloatingPoint): 126 (JSC::MacroAssemblerMIPS::supportsFloatingPointTruncate): 127 (JSC::MacroAssemblerMIPS::pop): 128 (JSC::MacroAssemblerMIPS::push): 129 (JSC::MacroAssemblerMIPS::move): 130 (JSC::MacroAssemblerMIPS::swap): 131 (JSC::MacroAssemblerMIPS::signExtend32ToPtr): 132 (JSC::MacroAssemblerMIPS::zeroExtend32ToPtr): 133 (JSC::MacroAssemblerMIPS::branch32): 134 (JSC::MacroAssemblerMIPS::branch32WithUnalignedHalfWords): 135 (JSC::MacroAssemblerMIPS::branch16): 136 (JSC::MacroAssemblerMIPS::branchTest32): 137 (JSC::MacroAssemblerMIPS::jump): 138 (JSC::MacroAssemblerMIPS::branchAdd32): 139 (JSC::MacroAssemblerMIPS::branchMul32): 140 (JSC::MacroAssemblerMIPS::branchSub32): 141 (JSC::MacroAssemblerMIPS::breakpoint): 142 (JSC::MacroAssemblerMIPS::nearCall): 143 (JSC::MacroAssemblerMIPS::call): 144 (JSC::MacroAssemblerMIPS::ret): 145 (JSC::MacroAssemblerMIPS::set32): 146 (JSC::MacroAssemblerMIPS::setTest32): 147 (JSC::MacroAssemblerMIPS::moveWithPatch): 148 (JSC::MacroAssemblerMIPS::branchPtrWithPatch): 149 (JSC::MacroAssemblerMIPS::storePtrWithPatch): 150 (JSC::MacroAssemblerMIPS::tailRecursiveCall): 151 (JSC::MacroAssemblerMIPS::makeTailRecursiveCall): 152 (JSC::MacroAssemblerMIPS::loadDouble): 153 (JSC::MacroAssemblerMIPS::storeDouble): 154 (JSC::MacroAssemblerMIPS::addDouble): 155 (JSC::MacroAssemblerMIPS::subDouble): 156 (JSC::MacroAssemblerMIPS::mulDouble): 157 (JSC::MacroAssemblerMIPS::convertInt32ToDouble): 158 (JSC::MacroAssemblerMIPS::insertRelaxationWords): 159 (JSC::MacroAssemblerMIPS::branchTrue): 160 (JSC::MacroAssemblerMIPS::branchFalse): 161 (JSC::MacroAssemblerMIPS::branchEqual): 162 (JSC::MacroAssemblerMIPS::branchNotEqual): 163 (JSC::MacroAssemblerMIPS::branchDouble): 164 (JSC::MacroAssemblerMIPS::branchTruncateDoubleToInt32): 165 (JSC::MacroAssemblerMIPS::linkCall): 166 (JSC::MacroAssemblerMIPS::repatchCall): 167 * jit/ExecutableAllocator.h: 168 (JSC::ExecutableAllocator::cacheFlush): 169 * wtf/Platform.h: 170 * yarr/RegexJIT.cpp: 171 (JSC::Yarr::RegexGenerator::generateEnter): 172 (JSC::Yarr::RegexGenerator::generateReturn): 173 1 174 2010-03-03 Steve Falkenburg <sfalken@apple.com> 2 175 -
trunk/JavaScriptCore/assembler/AbstractMacroAssembler.h
r52729 r55500 174 174 explicit Imm32(int32_t value) 175 175 : m_value(value) 176 #if CPU(ARM) 176 #if CPU(ARM) || CPU(MIPS) 177 177 , m_isPointer(false) 178 178 #endif … … 183 183 explicit Imm32(ImmPtr ptr) 184 184 : m_value(ptr.asIntptr()) 185 #if CPU(ARM) 185 #if CPU(ARM) || CPU(MIPS) 186 186 , m_isPointer(true) 187 187 #endif … … 191 191 192 192 int32_t m_value; 193 #if CPU(ARM) 193 #if CPU(ARM) || CPU(MIPS) 194 194 // We rely on being able to regenerate code to recover exception handling 195 195 // information. Since ARMv7 supports 16-bit immediates there is a danger … … 198 198 // from ImmPtrs) with a code sequence that is able to represent any pointer 199 199 // value - don't use a more compact form in these cases. 200 // Same for MIPS. 200 201 bool m_isPointer; 201 202 #endif -
trunk/JavaScriptCore/assembler/MacroAssembler.h
r52729 r55500 39 39 namespace JSC { typedef MacroAssemblerARM MacroAssemblerBase; }; 40 40 41 #elif CPU(MIPS) 42 #include "MacroAssemblerMIPS.h" 43 namespace JSC { 44 typedef MacroAssemblerMIPS MacroAssemblerBase; 45 }; 46 41 47 #elif CPU(X86) 42 48 #include "MacroAssemblerX86.h" -
trunk/JavaScriptCore/jit/ExecutableAllocator.h
r52822 r55500 44 44 #endif 45 45 46 #if CPU(MIPS) && OS(LINUX) 47 #include <sys/cachectl.h> 48 #endif 49 46 50 #if OS(WINCE) 47 51 // From pkfuncs.h (private header file from the Platform Builder) … … 190 194 static void cacheFlush(void*, size_t) 191 195 { 196 } 197 #elif CPU(MIPS) 198 static void cacheFlush(void* code, size_t size) 199 { 200 #if COMPILER(GCC) && (GCC_VERSION >= 40300) 201 #if WTF_MIPS_ISA_REV(2) && (GCC_VERSION < 40403) 202 int lineSize; 203 asm("rdhwr %0, $1" : "=r" (lineSize)); 204 // 205 // Modify "start" and "end" to avoid GCC 4.3.0-4.4.2 bug in 206 // mips_expand_synci_loop that may execute synci one more time. 207 // "start" points to the fisrt byte of the cache line. 208 // "end" points to the last byte of the line before the last cache line. 209 // Because size is always a multiple of 4, this is safe to set 210 // "end" to the last byte. 211 // 212 intptr_t start = reinterpret_cast<intptr_t>(code) & (-lineSize); 213 intptr_t end = ((reinterpret_cast<intptr_t>(code) + size - 1) & (-lineSize)) - 1; 214 __builtin___clear_cache(reinterpret_cast<char*>(start), reinterpret_cast<char*>(end)); 215 #else 216 intptr_t end = reinterpret_cast<intptr_t>(code) + size; 217 __builtin___clear_cache(reinterpret_cast<char*>(code), reinterpret_cast<char*>(end)); 218 #endif 219 #else 220 _flush_cache(reinterpret_cast<char*>(code), size, BCACHE); 221 #endif 192 222 } 193 223 #elif CPU(ARM_THUMB2) && OS(IPHONE_OS) -
trunk/JavaScriptCore/wtf/Platform.h
r55117 r55500 105 105 #endif 106 106 107 /* CPU(MIPS) - MIPS 32-bit */ 108 /* Note: Only O32 ABI is tested, so we enable it for O32 ABI for now. */ 109 #if (defined(mips) || defined(__mips__)) \ 110 && defined(_ABIO32) 111 #define WTF_CPU_MIPS 1 112 #if defined(__MIPSEB__) 113 #define WTF_CPU_BIG_ENDIAN 1 114 #endif 115 #define WTF_MIPS_PIC (defined __PIC__) 116 #define WTF_MIPS_ARCH __mips 117 #define WTF_MIPS_ISA(v) (defined WTF_MIPS_ARCH && WTF_MIPS_ARCH == v) 118 #define WTF_MIPS_ISA_AT_LEAST(v) (defined WTF_MIPS_ARCH && WTF_MIPS_ARCH >= v) 119 #define WTF_MIPS_ARCH_REV __mips_isa_rev 120 #define WTF_MIPS_ISA_REV(v) (defined WTF_MIPS_ARCH_REV && WTF_MIPS_ARCH_REV == v) 121 #define WTF_MIPS_DOUBLE_FLOAT (defined __mips_hard_float && !defined __mips_single_float) 122 #endif /* MIPS */ 123 107 124 /* CPU(PPC) - PowerPC 32-bit */ 108 125 #if defined(__ppc__) \ … … 831 848 #if (CPU(X86_64) && (OS(UNIX) || OS(WINDOWS))) || CPU(IA64) || CPU(ALPHA) 832 849 #define WTF_USE_JSVALUE64 1 833 #elif CPU(ARM) || CPU(PPC64) 850 #elif CPU(ARM) || CPU(PPC64) || CPU(MIPS) 834 851 #define WTF_USE_JSVALUE32 1 835 852 #elif OS(WINDOWS) && COMPILER(MINGW) … … 951 968 || (CPU(X86) && OS(LINUX) && GCC_VERSION >= 40100) \ 952 969 || (CPU(X86_64) && OS(LINUX) && GCC_VERSION >= 40100) \ 953 || (CPU(ARM_TRADITIONAL) && OS(LINUX)) 970 || (CPU(ARM_TRADITIONAL) && OS(LINUX)) \ 971 || (CPU(MIPS) && OS(LINUX)) 954 972 #define ENABLE_YARR 1 955 973 #define ENABLE_YARR_JIT 1 -
trunk/JavaScriptCore/yarr/RegexJIT.cpp
r52729 r55500 55 55 56 56 static const RegisterID returnRegister = ARMRegisters::r0; 57 #elif CPU(MIPS) 58 static const RegisterID input = MIPSRegisters::a0; 59 static const RegisterID index = MIPSRegisters::a1; 60 static const RegisterID length = MIPSRegisters::a2; 61 static const RegisterID output = MIPSRegisters::a3; 62 63 static const RegisterID regT0 = MIPSRegisters::t4; 64 static const RegisterID regT1 = MIPSRegisters::t5; 65 66 static const RegisterID returnRegister = MIPSRegisters::v0; 57 67 #elif CPU(X86) 58 68 static const RegisterID input = X86Registers::eax; … … 1314 1324 push(ARMRegisters::r6); 1315 1325 move(ARMRegisters::r3, output); 1326 #elif CPU(MIPS) 1327 // Do nothing. 1316 1328 #endif 1317 1329 } … … 1331 1343 pop(ARMRegisters::r5); 1332 1344 pop(ARMRegisters::r4); 1345 #elif CPU(MIPS) 1346 // Do nothing 1333 1347 #endif 1334 1348 ret();
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