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- [192508]: [JSC] Make FTLOutput's load8() and load16() compatible with B3 ...
- ... org/show_bug.cgi?id=151336 Patch by Benjamin Poulain <bpoulain@apple.com> on 2015-11-16 Reviewed by Filip Pizlo. B3 does not have 8bit and 16bit types. Make FTLOutput abstract enough to handle LLVM IR and B3. * ftl/FTLLowerDFGToLLVM.cpp: (JSC::FTL::DFG::LowerDFGToLLVM::compileGetArrayLength) ...
- By Nov 16, 2015 10:20:21 PM —
- [192498]: Fix a typo in AirIteratedRegisterCoalescing I forgot to fix that ...
- ... Patch by Benjamin Poulain <bpoulain@apple.com> on 2015-11-16 * b3/air/AirIteratedRegisterCoalescing.cpp: (JSC::B3::Air::IteratedRegisterCoalescingAllocator::build):
- By Nov 16, 2015 4:53:05 PM —
- [192497]: [JSC] Add support for the extra registers that can be clobbered by ...
- ... org/show_bug.cgi?id=151246 Patch by Benjamin Poulain <bpoulain@apple.com> on 2015-11-16 Reviewed by Geoffrey Garen. Specials can clobber arbitrary registers. This was not handled correctly by Air and nothing was preventing us from re-allocating those registers. This patch adds support for th ...
- By Nov 16, 2015 4:44:28 PM —
- [192493]: [JSC] Add trivial lowering for B3's Div with doubles ...
- ... org/show_bug.cgi?id=151292 Patch by Benjamin Poulain <bpoulain@apple.com> on 2015-11-16 Reviewed by Geoffrey Garen. Filip had already made the constant propagation for it. The Air Opcode was all we had left. * b3/B3LowerToAir.cpp: (JSC::B3::Air::LowerToAir::lower): * b3/air/AirOpcode.opcodes ...
- By Nov 16, 2015 3:49:22 PM —
- [192492]: [JSC] Speed up the coalescing-related operation of the iterated ...
- ... org/show_bug.cgi?id=151290 Patch by Benjamin Poulain <bpoulain@apple.com> on 2015-11-16 Reviewed by Geoffrey Garen. One step closer to removing the Hash structures: For the coalescing operation, we need to keep track of Move instructions. We do not strictly need those to be the Air Move, jus ...
- By Nov 16, 2015 3:47:10 PM —
- [192409]: [JSC] Do not generate an Add when adding a zero immediate to something ...
- ... org/show_bug.cgi?id=151171 Patch by Benjamin Poulain <bpoulain@apple.com> on 2015-11-12 Reviewed by Geoffrey Garen. Avoid generating an add if one of arguments is a zero immediate. On x86, the add32/64() were also used internally for branchAdd32/64. I split the code that sets flag to add32An ...
- By Nov 12, 2015 10:13:11 PM —
- [192355]: [JSC] Air: we have more register than what the allocator believed ...
- ... org/show_bug.cgi?id=151182 Patch by Benjamin Poulain <bpoulain@apple.com> on 2015-11-11 Reviewed by Michael Saboff. I was using GPRInfo/FPRInfo to get the number of register while coloring the interference graph. The problem is, those classes are lying about register availability. They don't ...
- By Nov 11, 2015 11:38:00 PM —
- [192348]: [JSC] Add a comment explaining the opcode suffixes on x86 ...
- ... org/show_bug.cgi?id=151176 Patch by Benjamin Poulain <bpoulain@apple.com> on 2015-11-11 Reviewed by Alex Christensen. * assembler/X86Assembler.h: I was always confused with the prefixes. Gavin pointed out the Intel documentation explains everything. I added a comment to help the next person c ...
- By Nov 11, 2015 9:19:40 PM —
- [192347]: [JSC] Support Doubles with B3's Add ...
- ... org/show_bug.cgi?id=151164 Patch by Benjamin Poulain <bpoulain@apple.com> on 2015-11-11 Reviewed by Filip Pizlo. I tweaked ReduceStrength a bit to maintain correctness. Nothing fancy otherwise. * b3/B3LowerToAir.cpp: (JSC::B3::Air::LowerToAir::lower): * b3/B3ReduceStrength.cpp: * b3/B3Value. ...
- By Nov 11, 2015 9:12:20 PM —
- [192292]: Air should allocate registers ...
- ... org/show_bug.cgi?id=150457 Patch by Benjamin Poulain <bpoulain@apple.com> on 2015-11-10 Reviewed by Filip Pizlo. This is a direct implementation of the Iterated Register Coalescing allocator. * JavaScriptCore.xcodeproj/project.pbxproj: * b3/air/AirGenerate.cpp: (JSC::B3::Air::generate): * b3 ...
- By Nov 10, 2015 9:10:43 PM —
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